參數(shù)資料
型號: ZPSD813F1V
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲器,256K位EEPROM,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬位閃速存儲器,256K位的EEPROM,16K的位的SRAM)
文件頁數(shù): 2/130頁
文件大?。?/td> 650K
代理商: ZPSD813F1V
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PSD813F Famly
PSD813F ZPSD813F ZPSD813FV
Flash In-SystemProgrammable Microcontroller Peripherals
Table of Contents
1.0
2.0
Introduction...........................................................................................................................................................1
Key Features ........................................................................................................................................................2
PSD813F Block Diagram ...............................................................................................................................4
General Information..............................................................................................................................................5
PSD813F Family...................................................................................................................................................5
PSD813F Architectural Overview .........................................................................................................................6
5.1 Memory...................................................................................................................................................6
5.2 Page Register.........................................................................................................................................6
5.3 PLDs.......................................................................................................................................................6
5.4 I/O Ports..................................................................................................................................................7
5.5 Microcontroller Bus Interface..................................................................................................................7
5.6 JTAG Port...............................................................................................................................................7
5.7 In-System Programming.........................................................................................................................8
5.8 Power Management................................................................................................................................8
Development System............................................................................................................................................9
PSD813F Pin Descriptions .................................................................................................................................10
PSD813F Register Description and Address Offset...........................................................................................14
PSD813F Functional Blocks...............................................................................................................................15
9.1 Memory Blocks .....................................................................................................................................15
9.1.1 Main Flash and Optional Secondary EEPROM or Flash Boot Memory Description..................15
9.1.2 SRAM.........................................................................................................................................30
9.1.3 Memory Select Signals...............................................................................................................30
9.1.4 Page Register.............................................................................................................................35
9.2 PLDs.....................................................................................................................................................36
9.2.1 Decode PLD (DPLD)..................................................................................................................38
9.2.2 Complex PLD (CPLD)................................................................................................................38
9.3 Microcontroller Bus Interface................................................................................................................47
9.3.1 Interfacing 16-bit MCUs with Two PSD813F Devices................................................................47
9.3.2 PSD813F Interface to a Multiplexed 8-bit Bus ...........................................................................47
9.3.3 PSD813F Interface to a Non-Multiplexed 8-bit Bus....................................................................47
9.3.4 Data Byte Enable Reference......................................................................................................50
9.3.5 Microcontroller Interface Examples............................................................................................50
9.4 I/O Ports................................................................................................................................................55
9.4.1 General Port Architecture...........................................................................................................55
9.4.2 Port Operating Modes................................................................................................................57
9.4.3 Port Configuration Registers (PCRs) .........................................................................................60
9.4.4 Port Data Registers....................................................................................................................63
9.4.5 Ports A and B – Functionality and Structure ............................................................................64
9.4.6 Port C – Functionality and Structure ........................................................................................66
9.4.7 Port D – Functionality and Structure ........................................................................................66
9.5 Power Management..............................................................................................................................70
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode .....................................................70
9.5.2 Other Power Saving Options......................................................................................................74
9.5.3 Reset Input.................................................................................................................................75
3.0
4.0
5.0
6.0
7.0
8.0
9.0
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