- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382773 > ZPSD813F1V Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | ZPSD813F1V |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位閃速存儲(chǔ)器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁(yè)數(shù)： | 33/130頁(yè) |
| 文件大小： | 650K |
| 代理商： | ZPSD813F1V |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)
Prelimnary
PSD813F Famly
29
The
PSD813F
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Protection Register
9.1.1.9.2 Reset Instruction
The Reset instruction resets the internal memory logic state machine in a few milliseconds.
Reset is an instruction of either one write operation or three write operations (refer to
Table 9).
9.1.1.9.3 Programmng and Erasing the Boot Blocks in PSD813F2 and PSD813F4
There are two different algorithms for programming and erasing the Boot Blocks in the
PSD813F2 and F4 (Boot Blocks are selected by CSBOOTi). The selection of the correct
algorithm is based on the internal die of the PSD device, which can be identified based on
the Flash Memory Identifier read by the MCU. Using the Read Flash Identifier instruction
(Table 9), the MCU will read one of two IDs for the PSD813F2 and PSD813F4, as shown in
Table 12.
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
PSD/EE Protection Register
1 = Flash or Flash Boot Sector <i> is write protected.
0 = Flash or Flash Boot Sector <i> is not write protected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_
Bit
*
*
*
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
Security_Bit
1 = EEPROM or Flash Boot Sector <i> is write protected.
0 = EEPROM or Flash Boot Sector <i> is not write protected.
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Device
Flash ID
E3h
E4h
Boot Block Algorithm
EEPROM Algorithm (See Section 9.1.1.6)
Flash Algorithm (See Section 9.1.1.7)
PSD813F2 and F4
PSD813F2 and F4
Table 12. Flash Memory IDValues for PSD813F2 and F4
For users of the PSD813F2 and F4, the MCU system software must make both algorithms
available. Within the routine that programs or erases the Boot Block area, the MCU should
use the Flash Memory Identifier first to select the appropriate algorithm. If the Identifier is
E4h, then it should treat the Boot Block area as Flash memory. If the Identifier is E3h, then
the MCU should treat the Boot Block area as EEPROM. This will ensure compatibility with
all future PSD813F2 and F4 devices.
Note:
The MCU must not operate out of Main Flash while reading the Flash Memory
Identifier. It can execute the Flash Memory Identifier command from some other memory,
and store the ID value for later use.
This algorithm selection method only applies to the PSD813F2 and F4. The PSD813F1 will
always use the EEPROM algorithm for the Boot Block area. The PSD813F3 and F5 have
no Boot Block area.
Note that this algorithm selection method is not required when programming or erasing the
main Flash memory. It only applies to programming or erasing the Boot Block area.
Main Flash will always require the Flash algorithm defined in section 9.1.1.7, regardless of
internal die composition.
Table 11. Sector Protection/Security Bit Definition
*:
Not used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR33771GC-40 | Cell Rectifier Diodes |
| ZR33771GM-20 | Cell Rectifier Diodes |
| ZR33771GM-30 | Cell Rectifier Diodes |
| ZR33771GM-40 | Cell Rectifier Diodes |
| ZR33771PQC-20 | Cell Rectifier Diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD813F1V-15J | 制造商:WSI 功能描述: |
| ZPSD813F1V-15J-CC790 | 制造商:STMicroelectronics 功能描述:Flash In SystemProgrammable Mirocomputer Peripherals |
| ZPSD813F1V-20J | 制造商:WSI 功能描述: |
| ZPSD813F2-12JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| ZPSD813F2-12UI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。