參數(shù)資料
型號: ZPSD813F1V
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲器,256K位EEPROM,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(shè)(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬位閃速存儲器,256K位的EEPROM,16K的位的SRAM)
文件頁數(shù): 106/130頁
文件大小: 650K
代理商: ZPSD813F1V
PSD813F Family
Preliminary
102
-15
-20
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVDV
ALE Access Time from
Power Down
150
200
ns
Maximum Delay from APD Enable
to Internal PDN Valid Signal
t
CLWH
Using CLKIN Input
15
*
t
CLCL
(Note 1)
μs
Power Down Timing
(2.7 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
NLNH
Warm RESET Active Low Time (Note 1)
300
ns
t
OPR
RESET High to Operational Device
300
ns
t
NLNH-PO
Power On Reset Active Low Time
(Note 2)
1
ms
Reset Timing
(2.7 V to 3.6 V Versions)
NOTE:
1. t
CLCL
is the CLKIN clock period.
Microcontroller Interface – ZPSD813FV AC/DC Parameters
(2.7 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
VstbyDetection to VstbyonOutput
High
2.0
μs
t
BXBL
VstbyOff Detection to Vstbyon
Output Low
2.0
μs
V
stbyon
Timing
(2.7 V to 3.6 V Versions)
NOTE:
1. RESET will not reset Flash or EEPROM programming/erase cycles.
2. tNLNH-PO is 10 ms for devices manufactured before the rev. A.
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