
xr
XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
187
2.2.6.8
THE TRANSMIT CELL INSERTION BUFFER/PROCESSOR
The Transmit ATM Cell Processor block consists of a “Transmit Cell Insertion Buffer/Processor” block.
Figure24 presents the functional block diagram of the Transmit ATM Cell Processor block with the “Transmit Cell
Insertion Buffer/Processor” block highlighted.
Figure 24: Illustration of the Transmit ATM Cell Processor block Functional Block Diagram, with the
“Transmit Cell Insertion Buffer/Processor” block highlighted
Parity
Checker
Block
Parity
Checker
Block
User Cell
Filter
Block
User Cell
Filter
Block
Cell Extraction
Buffer/
Processor
Cell Extraction
Buffer/
Processor
Cell Insertion
Buffer/
Processor
Cell Insertion
Buffer/
Processor
HEC Byte
Calculation
&
Insertion
Block
HEC Byte
Calculation
&
Insertion
Block
Cell Payload
Scrambler
Block
Cell Payload
Scrambler
Block
TxFIFO
Transmit UTOPIA
Interface Block
Microprocessor
Interface
Block
Microprocessor
Interface
Block
Idle Cell
Generator
Idle Cell
Generator
Main Data Path
To Transmit
SONET/STS-3c
POH
Processor Block
Transmit GFC
Nibble-Field
Input Port
Block
Transmit GFC
Nibble-Field
Input Port
Block
TxGFC
Input Port
The Transmit Cell Insertion Buffer/Processor block permits the user to load the contents of an “outbound”
ATM cell into the “Transmit Cell Insertion Buffer” via the Microprocessor Interface. Once this cell has been
loaded into the “Transmit Cell Insertion Buffer”, then it will be transmitted to the remote terminal equipment
(via the Transmit Data Path) whenever the “TxFIFO” (within the Transmit UTOPIA Interface block) is depleted
of user cells.
An example of an application where this feature would be useful is in the loading and
transmission of OAM cells.
The Format of ATM Cell Data that is written into the “Transmit Cell Insertion” Buffer
As the user loads the contents of an ATM cell into the “Transmit Cell Insertion” Buffer (via the Microprocessor
Interface), they will be expected to write this ATM cell data into a 32 bit wide register/buffer interface. As a
consequence, the user must write in 56-byte size ATM cells into the “Transmit Cell Insertion” buffer.
The byte format of this 56 byte ATM cell is as illustrated below in
Figure 25.