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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
397
The user can configure the Receive STS-3 TOH Processor block to increment the “Receive SONET Path –
REI-P Error Count” Register by the contents within the “REI-P” nibbles, within each incoming STS-1 SPE.
Therefore, in this mode, it is possible for the Receive SONET POH Processor block to increment this register
by as much as the value “8” per STS-1 SPE.
The user can accomplish this by setting Bit 1 (REI-P Error Type) within the “Receive SONET Path –
Control Register – Byte 0” to “0”, as illustrated below.
Receive SONET Path – Control Register – Byte 0 (Address = 0xN183)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Check
Stuff
RDI-P
Type
REI-P
Error Type
B3 Error
Type
R/O
R/W
0
2.3.3.3
PATH BIP-8 (B3) BYTE VERIFICATION
Configuring the Receive SONET POH Processor block to increment the “Receive SONET Path – B3
Error Count” Register on a “per-SPE” basis.
The user can configure the Receive SONET POH Processor block to increment the “Receive SONET Path –
B3 Error Count” Register, by the value “1” for each STS-1 SPE that it determined to have a bit-error.
The user can accomplish this by setting Bit 0 (B3 Error Type), within the “Receive SONET Path – Control
Register – Byte 0” to “1”, as illustrated below.
Receive SONET Path – Control Register – Byte 0 (Address = 0xN183)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Check
Stuff
RDI-P
Type
REI-P
Error Type
B3 Error
Type
R/O
R/W
0
1
Note:
This the user implements this setting, then the corresponding Transmit SONET POH Processor block will set the
REI-P nibble value (within the G1 byte) to the number of erred SPE that have been detected. In this case, the
maximum value that the REI-P nibble (within an STS-1 SPE) will contain will be “1”.
The Receive SONET POH Processor block has the responsibility for computing and verifying the Path BIP-8
(e.g., B3) byte within each incoming STS-1 SPE. When the Receive SONET POH Processor block executes
this function, it will do the following.
It will read in the contents of a given “newly received” STS-1 SPE.
It will compute the BIP-8 value over the SPE.
This resulting BIP-8 value will be compared with the contents of the B3 byte, within the very next STS-1
SPE.
If the Receive SONET POH Processor block detects any B3 byte errors, then it will do the following.
a. It will generate the “Detection of B3 Error” Interrupt, by toggling the “INT*” output pin “LOW” and by
setting Bit 7 (Detection of B3 Byte Error Interrupt Status) to “1” as indicated below.