
XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
356
Receive STS-3 Transport Interrupt Status Register – Byte 2 (Address = 0x1109)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of
AIS-L Defect
Condition
Interrupt
Status
Change of
RDI-L
Defect
Condition
Interrupt
Status
R/O
RUR
0
1
2.3.1.6
DETECTING AND FLAGGING REI-L (LINE – REMOTE ERROR INDICATOR) EVENTS
The Receive STS-3 TOH Processor block is capable of detecting the REI-L indicator, within the incoming
STS-3 data-stream. As the Receive STS-3 TOH Processor block receives a given STS-3 data-stream, it will
monitor the contents within the M1 byte. The bit-format of the M1 byte is presented below in
Figure 88.Figure 88 Bit format of the M1 Byte
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
B2 Error Count (REI-L)
The role of the REI-L bit-fields was described in some detail, in Section _. This section indicates that the
remote terminal equipment will set the “REI-L” value (within the M1 byte) to “0” during “un-erred” conditions.
However, the remote terminal equipment will typically set the “REI-L” value to a value (ranging from “1” to
“24”) during “erred” conditions.
If the Receive STS-3 TOH Processor block receives an STS-3 frame, that contains a “non-zero” value of REI-
L, then it will do the following.
15. It will generate the “Detection of REI-L Error” Interrupt.
Note:
The Receive STS-3 TOH Processor block will indicate this by, pulling the “INT*” output pin “LOW” and by setting
Bit 5 (Detection of REI-L Error Interrupt Status), within the “Receive STS-3 Transport – Interrupt Status Register
– Byte 0” to “1” as depicted below.
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
SF Defect
Condition
Interrupt
Status
Change of
SD Defect
Condition
Interrupt
Status
Detection of
REI-L Error
Interrupt
Status
Detection of
B2 Byte
Error
Interrupt
Status
Detection of
B1 Byte
Error
Interrupt
Status
Change of
LOF Defect
Condition
Interrupt
Status
Change of
SEF Defect
Condition
Interrupt
Status
Change of
LOS Defect
Condition
Interrupt
Status
RUR
0
1
0
16. It will increment the “Receive STS-3 Transport – REI-L Error Count” Registers
Note:
These registers are actually 32-bit registers, which are located at Direct Address locations 0xNA19 through
0xNA1C. The bit-format of these registers is presented below.