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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
101
AE8
AE9
AG6
RxPOHClk_0
RxPOHClk_1
RxPOHClk_2
O
CMOS
Receive SONET POH Processor Block – Path Overhead
Output Port – Clock Output Signal:
These output pins, along with “RxPOH_n”, “RxPOHFrame_n” and
“RxPOHValid_n” function as the “Receive SONET POH Processor
block – POH Output Port.
These output pins function as the “Clock Output” signals for the
“Receive SONET POH Processor block – POH Output Port. The
“RxPOH_n”, “RxPOHFrame_n” and “RxPOHValid_n” output pins
are updated upon the falling edge of this clock signal.
As a
consequence, the external circuitry should sample these signals
upon the rising edge of this clock signal.
AF6
AD10
AE10
RxPOHFrame_0
RxPOHFrame_1
RxPOHFrame_2
O
CMOS
Receive SONET POH Processor Block – Path Overhead
Output Port – Frame Boundary Indicator:
These output pins, along with the “RxPOH_n”, RxPOHClk_n” and
“RxPOHValid_n” output pins function as the “Receive SONET POH
Processor Block – Path Overhead Output Port.
These output pins will pulse “high” coincident with the very first
POH byte (J1), of a given STS-1 frame, is being output via the
corresponding “RxPOH_n” output pin.
AC10
AF7
AC11
RxPOHValid_0
RxPOHValid_1
RxPOHValid_2
O
CMOS
Receive SONET POH Processor Block – Path Overhead
Output Port – Valid POH Data Indicator:
These output pins, along with “RxPOH_n”, “RxPOHClk_n” and
“RxPOHFrame_n”
function
as
the
“Receive
SONET
POH
Processor block – Path Overhead Output port.
These output pins will toggle “high” coincident with when valid POH
data is being output via the “RxPOH_n” output pins. This output is
updated upon the falling edge of RxPOHClk_n. Hence, external
circuitry should sample these signals upon rising edge of
“RxPOHClk_n”.
AD11
LOF
O
CMOS
Receive STS-3 LOF (Loss of Frame) Indicator:
This output pin indicates whether or not the Receive STS-3 TOH
Processor block (within the device) is currently declaring the LOF
defect condition as described below.
LOW – Indicates that the Receive STS-3 TOH Processor block is
NOT currently declaring the LOF defect condition.
HIGH – Indicates that the Receive STS-3 TOH Processor block is
currently declaring the LOF defect condition.
AF9
SEF
O
CMOS
Receive STS-3 SEF (Severed Errored Frame) Indicator:
This output pin indicates whether or not the Receive STS-3 TOH
Processor block (within the device) is currently declaring the SEF
defect condition as described below.
LOW – Indicates that the Receive STS-3 TOH Processor block is
NOT currently declaring the SEF defect condition.
HIGH – Indicates that the Receive STS-3 TOH Processor block is
currently declaring the SEF defect condition.