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xr
XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
15
STS-3/STM-1 TELECOM BUS INTERFACE – TRANSMIT DIRECTION
E1
TXA_CLK/
TxAPSCLK
O
I/O
CMOS
Transmit STS-3/STM-1 Telecom Bus Interface - Clock Output
Signal:
This output clock signal functions as the clock source for the
Transmit STS-3/STM-1 Telecom Bus. All signals, that are output
via the Transmit STS-3/STM-1 Telecom Bus Interface (e.g.,
TXA_C1J1, TXA_ALARM, TXA_DP, TXA_PL and TXA_D[7:0])
are updated upon the rising edge of this clock signal.
This clock signal operates at 19.44MHz and is derived from the
Clock Synthesizer block.
Transmit Payload APS Bus Interface Clock Input/Output
signal – TxAPSCLK:
This pin can only be configured to operate in this mode if the
XRT94L33 has been configured to operate in either the “ATM
UNI” over “PPP over STS-3c” Mode.
F2
TXA_C1J1
O
CMOS
Transmit STS-3/STM-1 Telecom Bus Interface - C1/J1 Byte
Phase Indicator Output Signal:
This output pin pulses “high” under the following two conditions.
Whenever the C1 byte is being output via the “TxA_D[7:0]”
output, and
Whenever the J1 byte is being output via the “TxA_D[7:0]”
output.
Notes:
1.
The Transmit STS-3/STM-1 Telecom Bus Interface will
indicate that it is currently transmitting the C1 byte (via the
TXA_D[7:0] output pins), by pulsing this output pin “HIGH”
(for one period of “TXA_CLKTXA_CK”) and keeping the
“TXA_PL” output pin pulled “LOW”.
2.
The Transmit STS-3/STM-1 Telecom Bus will indicate that it
is currently transmitting the J1 byte (via the TXA_D[7:0]
output pins), by pulsing this output pin “HIGH” (for one
period of “TXA_CLKTXA_CK”) while the “TXA_PL” output
pin is pulled “HIGH”.
3.
This output pin is only active if the Transmit STS-3/STM-1
Telecom Bus Interface block is enabled and is configured to
operate in the “Re-Phase OFF” Mode.