
XRT84L38
V
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
R
ECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER
(RICR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
22H) ........................ 227
5.1.3.1 T1 R
ECEIVE
I
NPUT
I
NTERFACE
- MVIP 2.048 MH
Z
.............................................................................................. 227
T
ABLE
45: T
HE
MAPPING
OF
T1
FRAME
INTO
E1
FRAMING
FORMAT
................................................................................................ 228
F
IGURE
49. I
NTERFACING
XRT84L38
TO
LOCAL
T
ERMINAL
E
QUIPMENT
USING
MVIP 2.048M
BIT
/
S
D
ATA
B
US
................................ 229
F
IGURE
50. T
IMING
D
IAGRAM
OF
I
NPUT
SIGNALS
TO
THE
F
RAMER
WHEN
RUNNING
AT
MVIP 2.048M
BIT
/
S
...................................... 229
5.1.3.2 T1 R
ECEIVE
I
NPUT
I
NTERFACE
- 4.096 MH
Z
....................................................................................................... 229
T
ABLE
46: T
HE
MAPPING
OF
T1
FRAME
INTO
E1
FRAMING
FORMAT
................................................................................................ 230
F
IGURE
51. I
NTERFACING
XRT84L38
TO
LOCAL
T
ERMINAL
E
QUIPMENT
USING
4.096M
BIT
/
S
D
ATA
B
US
......................................... 231
F
IGURE
52. T
IMING
D
IAGRAM
OF
I
NPUT
SIGNALS
TO
THE
F
RAMER
WHEN
RUNNING
AT
4.096M
BIT
/
S
................................................ 231
5.1.3.3 T1 R
ECEIVE
I
NPUT
I
NTERFACE
- 8.192 MH
Z
....................................................................................................... 231
T
ABLE
47: T
HE
MAPPING
OF
T1
FRAME
INTO
E1
FRAMING
FORMAT
................................................................................................ 232
F
IGURE
53. I
NTERFACING
XRT84L38
TO
LOCAL
T
ERMINAL
E
QUIPMENT
USING
8.192M
BIT
/
S
D
ATA
B
US
......................................... 233
F
IGURE
54. T
IMING
D
IAGRAM
OF
I
NPUT
SIGNALS
TO
THE
F
RAMER
WHEN
RUNNING
AT
8.192M
BIT
/
S
................................................ 233
5.1.3.4 T1 R
ECEIVE
I
NPUT
I
NTERFACE
- M
ULTIPLEXED
12.352M
BIT
/
S
............................................................................. 233
F
IRST
O
CTET
OF
12.352M
BIT
/
S
D
ATA
S
TREAM
.......................................................................................... 234
S
ECOND
O
CTET
OF
12.352M
BIT
/
S
D
ATA
S
TREAM
...................................................................................... 234
T
HIRD
O
CTET
OF
12.352M
BIT
/
S
D
ATA
S
TREAM
......................................................................................... 234
S
IXTH
O
CTET
OF
12.352M
BIT
/
S
D
ATA
S
TREAM
......................................................................................... 235
S
EVENTH
O
CTET
OF
12.352M
BIT
/
S
D
ATA
S
TREAM
.................................................................................... 235
E
IGHTH
O
CTET
OF
12.352M
BIT
/
S
D
ATA
S
TREAM
....................................................................................... 235
N
INETH
O
CTET
OF
12.352M
BIT
/
S
D
ATA
S
TREAM
....................................................................................... 235
F
IGURE
55. I
NTERFACING
XRT84L38
TO
LOCAL
T
ERMINAL
E
QUIPMENT
USING
12.352M
BIT
/
S
D
ATA
B
US
....................................... 236
F
IGURE
56. T
IMING
D
IAGRAM
OF
I
NPUT
SIGNALS
TO
THE
F
RAMER
WHEN
RUNNING
AT
12.352M
BIT
/
S
.............................................. 236
5.1.3.5 T1 R
ECEIVE
I
NPUT
I
NTERFACE
- B
IT
-M
ULTIPLEXED
16.384M
BIT
/
S
....................................................................... 236
F
IRST
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.......................................................................................... 237
N
INTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
......................................................................................... 237
T
ENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
........................................................................................ 237
T
HIRTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
................................................................................ 238
F
OURTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.............................................................................. 238
F
IFTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.................................................................................. 238
S
IXTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.................................................................................. 238
F
IGURE
57. I
NTERFACING
XRT84L38
TO
LOCAL
T
ERMINAL
E
QUIPMENT
USING
16.384M
BIT
/
S
D
ATA
B
US
....................................... 239
F
IGURE
58. T
IMING
D
IAGRAM
OF
I
NPUT
SIGNALS
TO
THE
F
RAMER
WHEN
RUNNING
AT
B
IT
-
MULTIPLEXED
16.384M
BIT
/
S
................... 239
5.1.3.6 T1 R
ECEIVE
I
NPUT
I
NTERFACE
- HMVIP 16.384M
BIT
/
S
....................................................................................... 239
IRST
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.......................................................................................... 240
N
INTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
......................................................................................... 240
E
LEVENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
................................................................................... 240
T
HIRTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
................................................................................ 241
F
IFTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.................................................................................. 241
T
ENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
........................................................................................ 241
T
WELFTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
F
OURTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.............................................................................. 241
S
IXTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.................................................................................. 241
F
IGURE
59. I
NTERFACING
XRT84L38
TO
LOCAL
T
ERMINAL
E
QUIPMENT
USING
16.384M
BIT
/
S
D
ATA
B
US
....................................... 242
F
IGURE
60. T
IMING
D
IAGRAM
OF
I
NPUT
SIGNALS
TO
THE
F
RAMER
WHEN
RUNNING
AT
HMVIP 16.384M
BIT
/
S
.................................. 243
5.1.3.7 T1 R
ECEIVE
I
NPUT
NTERFACE
- H.100 16.384M
BIT
/
S
......................................................................................... 243
F
IRST
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.......................................................................................... 243
N
INTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
......................................................................................... 244
E
LEVENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
................................................................................... 244
T
HIRTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
................................................................................ 244
F
IFTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.................................................................................. 244
T
ENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
........................................................................................ 245
T
WELFTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.................................................................................... 245
F
OURTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.............................................................................. 245
S
IXTEENTH
O
CTET
OF
16.384M
BIT
/
S
D
ATA
S
TREAM
.................................................................................. 245
F
IGURE
61. I
NTERFACING
XRT84L38
TO
LOCAL
T
ERMINAL
E
QUIPMENT
USING
H.100 16.384M
BIT
/
S
D
ATA
B
US
............................. 246
F
IGURE
62. T
IMING
D
IAGRAM
OF
I
NPUT
SIGNALS
TO
THE
F
RAMER
WHEN
RUNNING
AT
H.100 16.384M
BIT
/
S
................................... 246
6.0 THE E1 TRANSMIT SECTION ............................................................................................................ 247
6.1 THE E1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK............................................................. 247