
XRT84L38
345
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
3.
Each 6 ms interval with a valid AIS flag increments a flag counter which declares AIS alarm when 255 valid
flags have been collected.
Therefore, AIS condition has to be persisted for 1.53 seconds before AIS alarm condition is declared by the
XRT84L38 framer.
If there is no valid AIS flag over a 6ms interval, the Alarm indication logic will decrement the flag counter. The
AIS alarm is removed when the counter reaches 0. That is, AIS alarm will be removed if over 1.53 seconds,
there is no valid AIS flag.
The Alarm Indication Signal Detection Select [1:0] bits of the Alarm Generation Register (AGR) enable the two
types of AIS detection that are supported by the XRT84L38 framer. The table below shows configurations of
the Alarm Indication Signal Detection Select [1:0] bits of the Alarm Generation Register (AGR).
ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H)
If detection of unframed or framed AIS alarm is enabled by the user and if AIS is present in the incoming DS1
frame, the XRT84L38 framer can generate a Receive AIS State Change interrupt associated with the setting of
Receive AIS State Change bit of the Alarm and Error Status Register to one.
To enable the Receive AIS State Change interrupt, the Receive AIS State Change Interrupt Enable bit of the
Alarm and Error Interrupt Enable Register (AEIER) have to be set to one. In addition, the Alarm and Error
Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive AIS State Change Interrupt Enable bit of the Alarm and
Error Interrupt Enable Register (AEIER).
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH,
0X03H)
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H)
When these interrupt enable bits are set and AIS is present in the incoming DS1 frame, the XRT84L38 framer
will declare AIS by doing the following:
Set the read-only Receive AIS State bit of the Alarm and Error Status Register (AESR) to one indicating
there is AIS alarm detected in the incoming DS1 frame.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1-0
AIS Detection
Select
R/W
00 - AIS alarm detection is disabled.When this bit is set to 01:Detection of
unframed AIS alarm of all ones pattern is enabled.
10 - AIS alarm detection is disabled.When this bit is set to 00:Detection of
framed AIS alarm of all ones pattern except for framing bits is enabled.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Receive AIS State
Change Interrupt
Enable
R/W
0 - The Receive AIS State Change interrupt is disabled.
1 - The Receive AIS State Change interrupt is enabled.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.