
XRT84L38
376
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
When the Receive Data Conditioning Select [3:0] bits of the Receive Channel Control Register (RCCR) of a
particular DS0 channel are set to 0100, the received E1 payload data of this DS0 channel are replaced by the
octet stored in the Receive User IDLE Code Register (RUCR). The table below shows contents of the Receive
User IDLE Code Register.
RECEIVE USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X97H)
12.4
How to Configure the XRT84L38 Framer to Extract Robbed-bit Signaling Information
The XRT84L38 T1/J1/E1 Octal Framer supports insertion of Robbed-bit Signaling information into the outgoing
E1 frame. It also supports extraction and substitution of Robbed-bit Signaling information from the incoming E1
frame. The following section describes how does the XRT84L38 framer extract and substitute Robbed-bit
Signaling in E1 mode.
12.4.1
Configure the framer to receive and extract Robbed-bit Signaling
The XRT84L38 framer supports receiving and extraction of CAS signaling. The Receive Signaling Extraction
Control [1:0] bits of the Receive Signaling Control Register (RSCR) of each channel select either:
No signaling extraction
Two-code signaling
Four-code signaling or
Sixteen-code signaling
The table below shows configurations of the Receive Signaling Extraction Control [1:0] bits of the Receive
Signaling Control Register.
RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XB7H)
Upon receiving and extraction of signaling bits from the incoming E1 frames, the XRT84L38 framer compares
the signaling bits with the previously received ones. If there is a change of signaling data, a Signaling Update
(SIG) interrupt request may be generated at the end of an E1 multi-frame. The user can thus be notified of a
Change of Signaling Data event.
To enable the Signaling Update interrupt, the Signaling Change Interrupt Enable bit of the Framer Interrupt
Enable Register (FIER) has to be set. In addition, the T1/E1 Framer Interrupt Enable bit of the Block Interrupt
Enable Register (BIER) needs to be one.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
7-0
User IDLE Code
R/W
These READ/WRITE bit-fields permits the user store any value of IDLE
code into the framer. When the Receive Data Conditioning Select [3:0] bits
of RCCR register of a particular DS0 channel are set to 0100, the received
E1 payload data are replaced by contents of this register and sent to the
Terminal Equipment.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1-0
Signaling
Extraction Control
R/W
00 - The XRT84L38 framer does not extract signaling information from
incoming E1 payload data.
01 - The XRT84L38 framer extracts sixteen-code signaling information
from incoming E1 payload data.
10 - The XRT84L38 framer extracts four-code signaling information from
incoming E1 payload data.
11 - The XRT84L38 framer extracts two-code signaling information from
incoming E1 payload data.