
XRT84L38
XIII
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
T
RANSMIT
D
ATA
L
INK
S
ELECT
R
EGISTER
(TSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0AH).................... 393
13.1.3 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR.............................................................................. 393
13.1.3.1 D
ESCRIPTION
OF
BOS...................................................................................................................................... 393
13.1.3.2 H
OW
TO
CONFIGURE
THE
BOS P
ROCESSOR
B
LOCK
TO
TRANSMIT
BOS ............................................................ 393
T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
14H)............ 394
T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
14H)............ 394
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)....................................... 395
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 395
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)....................................... 395
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H)....................... 396
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(BIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
00H).............................. 396
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H) ........................................ 396
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 397
13.1.4 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) OR LAPD CONTROLLER.............................................. 397
F
IGURE
127. LAPD C
ONTROLLER
................................................................................................................................................ 397
13.1.4.1 D
ISCUSSION
OF
MOS....................................................................................................................................... 398
F
IGURE
128. LAPD F
RAME
S
TRUCTURE
...................................................................................................................................... 398
13.1.4.2 H
OW
TO
CONFIGURE
THE
T
RANSMIT
HDLC C
ONTROLLER
B
LOCK
TO
TRANSMIT
MOS........................................ 401
T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
14H)............. 401
T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
14H)............ 402
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)....................................... 402
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)....................................... 402
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 403
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 403
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H)...................... 403
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(BIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
00H).............................. 404
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H) ........................................ 404
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 404
13.1.5 TRANSMIT SLC96 DATA LINK CONTROLLER ................................................................................................... 405
F
RAMING
S
ELECT
R
EGISTER
(FSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
07H).............................................. 405
T
RANSMIT
SLC96 M
ESSAGE
R
EGISTERS
................................................................................................ 406
13.1.5.1 H
OW
TO
CONFIGURE
THE
SLC96 D
ATA
L
INK
C
ONTROLLER
TO
TRANSMIT
SLC96 D
ATA
L
INK
M
ESSAGES
..... 406
T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
14H)............ 406
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H)....................... 407
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(BIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
00H)............................... 407
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H) ........................................ 408
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 408
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 408
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 408
13.2 DS1 RECEIVE HDLC CONTROLLER BLOCK............................................................................................. 409
13.2.1 DESCRIPTION OF THE DS1 RECEIVE HDLC CONTROLLER BLOCK................................................................. 409
R
ECEIVE
D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0CH) ..................... 409
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H)...................................... 410
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H) ........................................ 410
13.2.2 HOW TO CONFIGURE XRT84L38 TO RECEIVE DATA LINK INFORMATION THROUGH D OR E CHANNELS 410
R
ECEIVE
C
HANNEL
C
ONTROL
R
EGISTER
(RCCR) (I
NDIRECT
A
DDRESS
= 0
XN
2H, 0
X
60H - 0
X
7FH)........... 410
R
ECEIVE
D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0CH) ..................... 411
13.2.3 RECEIVE BOS (BIT ORIENTED SIGNALING) PROCESSOR................................................................................. 411
13.2.3.1 H
OW
TO
CONFIGURE
THE
BOS P
ROCESSOR
B
LOCK
TO
RECEIVE
BOS .............................................................. 411
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H)...................... 411
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(BIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
00H).............................. 412
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H) ........................................ 412
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H)...................... 412
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H) ........................................ 413
R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
15H)............... 413
R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
15H).............. 414
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H) ......................................... 414
13.2.4 RECEIVE LAPD CONTROLLER .............................................................................................................................. 414