
XRT84L38
402
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
The table below shows configurations of the Transmit Data Link Byte Count [6:0] bits the Transmit Data Link
Byte Count Register (TDLBCR).
TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H)
13.1.4.2.4
Step 4: Configure MOS Message transmission control bits
Configuration of the Data Link Control Register determines whether the LAPD Controller will insert IDLE flag
character, FCS or ABORT sequence to the data link channel. It also determines how the transition between
MOS mode to BOS mode is done.
If the IDLE Insertion bit of the Data Link Control Register is set, repeated flags of value 0x7E are transmitted as
soon as the current operation is finished (defined by the value in Transmit Data Link Byte Count Register). The
IDLE bit must be set to 1 at the last block of transfer to enable FCS and flag insertion for message completion.
The table below shows configurations of the IDLE Insertion bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
N
OTE
:
If the entire message is longer than 96-byte in length or more than one full block of message has to be transmitted,
the IDLE Insertion bit should not be set to one until the last block of message has to be sent.
If the FCS Insertion bit of the Data Link Control Register (DLCR) is set to high, the LAPD Controller will
calculate and insert the frame check sequence to the last block of the transmitted message.
The table below shows configurations of the FCS Insertion bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
If the FCS is not enabled at the end of a message, the controller will return to sending IDLE flags immediately
after the last octet is transmitted. This permits the use of a programmable FCS, which may be used for
diagnostic tests or other test applications.
To abort a transmitting message, the LAPD Controller sets the ABORT bit in Data Link Control Register to 1.
This bit is cleared after the LAPD transmitter finishes sending the message octet in progress. The transmitter
then transmit an ABORT sequence of one zero followed by seven ones (01111111) before goes to idle if the
IDLE bit is set. The transmitter will keep transmitting IDLE flag characters until it is instructed otherwise.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
6-0
Transmit Data Link
Byte Count [6:0]
R/W
Value of these bits determines length of the MOS message pattern to be
transmitted by the framer before generating the Transmit End of Transfer
(TxEOT) interrupt.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
2
IDLE Insertion
R/W
0 - No flag sequence is sent on the data link channel.
1 - The framer forces a flag sequence of value 0x7E onto the data link
channel.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
FCS Insertion
R/W
0 - No FCS will be inserted into the last block of the transmitted MOS mes-
sage.
1 - The LAPD Controller will calculate and insert the FCS into the last block
of the transmitted MOS message.