
XRT84L38
346
OCTAL T1/E1/J1 FRAMER
Set the Receive AIS State Change bit of the Alarm and Error Status Register to one indicating there is a
change in state of AIS. This status indicator is valid until the Framer Interrupt Status Register is read.
REV. 1.0.1
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive AIS State Change status bits of the Alarm and Error Status Register.
ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H)
The Receive AIS State bit of the Alarm and Error Status Register (AESR), on the other hand, is a read-only bit
indicating there is AIS alarm detected in the incoming DS1 frame.
The table below shows the Receive AIS State status bits of the Alarm and Error Status Register.
ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H)
10.6.2
How to configure the framer to detect Red Alarm
The Alarm indication logic within the Receive Framer block of the XRT84L38 framer monitors the incoming
DS1 frames for red alarm or Loss of Frame (LOF) condition. Red alarm condition are detected and declared
according to the following procedure:
1.
The red alarm is detected by monitoring the occurrence of Loss of Frame (LOF) over a 6 ms interval.
2.
An LOF valid flag will be posted on the interval when one or more LOF occurred during the interval.
3.
Each interval with a valid LOF flag increments a flag counter which declares RED alarm when 63 valid
intervals have been accumulated.
4.
An interval without valid LOF flag decrements the flag counter. The Red alarm is removed when the
counter reaches zero.
If LOF condition is present in the incoming DS1 frame, the XRT84L38 framer can generate a Receive Red
Alarm State Change interrupt associated with the setting of Receive Red Alarm State Change bit of the Alarm
and Error Status Register to one.
To enable the Receive Red Alarm State Change interrupt, the Receive Red Alarm State Change Interrupt
Enable bit of the Alarm and Error Interrupt Enable Register (AEIER) has to be set to one. In addition, the Alarm
and Error Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Receive AIS State
Change
RUR /
WC
0 - There is no change of AIS state in the incoming DS1 payload data.
1 - There is change of AIS state in the incoming DS1 payload data.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
6
Receive AIS State
R
0 - There is no AIS alarm condition detected in the incoming DS1 payload
data.
1 - There is AIS alarm condition detected in the incoming DS1 payload
data.