
XRT84L38
419
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
The result of the READ access should be 0xACH.
13.2.5
Receive SLCa96 Data link Controller
This section describes how to configure the Receive SLC96 Data Link Controller block to receive SLC96
Data Link message and how to read out the message from the receive data link message buffer. The operation
of the Receive SLC96 Data Link Controller is interrupt-driven. When a 36-bit SLC96 Data Link message is
received, message octet is written to the next receive data link message buffer opposite to that last used. The
receive SLC96 Data Link Controller generates interrupts to the microprocessor notifying it that a message is
received. The data link message can then be extracted from the appropriate receive data link buffer.
In order to enable this mode of operation, the framing mode must be set to SLC96. The XRT84L38 allocates
two 6-byte buffers to provide SLC96 Data Link Controller an alternating access mechanism for information
received. The bit ordering and usage is shown in the following table. The bits 7 and 6 are forced to 0 by the
SLC96 Data Link Controller.
RECEIVE SLC
96 MESSAGE REGISTERS
13.2.5.1
How to configure the SLC96 Data Link Controller to receive SLC96 Data Link Messages
This section describes how to configure the SLC96 Data Link Controller to receive SLC96 Data Link
message in a step-by-step basis.
The operation of the receive SLC96 Data Link Controller is interrupt-driven. When an SLC96 Data Link
message is receiving, message octets are written to the next receive data link message buffer opposite to that
last used. Every time the SLC96 Data Link controller receives a 36-bit SLC96 data link message, an
RxEOT interrupt is issued if it is enabled. This process continues until an ABORT sequence is received.
An interrupt is issued when one of the following conditions occurs and the corresponding interrupt enable bit is
set.
The RxSOT is set when the beginning of a data link message is received.
The RxEOT is set when the end of a data link block is received.
The RxABORT is set when an ABORT sequence is received.
13.2.5.1.1
Step 1: Enable receive SLC96 Data Link message interrupts
The receive SLC96 Data Link Controller can generate a couple of interrupts indicating the status of SLC96
message received to the microprocessor. These are the Receive Start of Transfer (RxSOT) interrupt and the
Receive End of Transfer (RxEOT) interrupt.
To enable these interrupts, the Receive Start of Transfer Enable bit and the Receive End of Transfer Enable bit
of the Data Link Interrupt Enable Register (DLIER) have to be set. In addition, the HDLC Controller Interrupt
Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
B
IT
B
YTE
7
6
5
4
3
2
1
0
1/7
0
0
0
1
1
1
0
0
2/8
0
0
C1
1
1
1
0
0
3/9
0
0
C7
C6
C5
C4
C3
C2
4/10
0
0
1
0
C11
C10
C9
C8
5/11
0
0
A2
A1
M3
M2
M1
0
6/12
0
0
0
1
S4
S3
S2
S1