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參數(shù)資料
| 型號(hào)： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁(yè)數(shù)： | 84/134頁(yè) |
| 文件大?。?/td> | 600K |
| 代理商： | TP6508 |
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P.81
Bit 5
When this bit is set to logical 1 , special palette snooping behavior is enabled . When this bit is reset
to logical 0 , the device should treat palette accesses like all other accesses .
This bit controls the device's response to data parity errors. When this bit is set, the devicem u s t
take its normal action when a parity error is detected. When this bit is reset, the device must ignore
any parity error that it detects and continue normal operation.
This bit is used to control whether or not a device does address/data stepping.
This bit is an enable bit for the SERR# driver. A logical 1 enables the SERR# driver and report ad-
dress parity error. A logical 0 disables the SERR# driver.
Implemented by bus masters only.
Reserved.
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10-15
Extended Index Register PREG Hex 06 : Status Register
This is a read/write register.
Default value after hardware reset is Hex 0280.
Port address is Hex CFC.
D0-4
D5
D6
D7
D8
D9-10
D11
D12
D13
D14
D15
(A write operation to this register can be reset, but not set.)
Reserved =0
66 MHz capable (read only =0)
UDF support (read only =0)
Fast Back-to-Back capable (read only =1)
Data Parity Error Detected (reserved =0)
DEVSEL# timing (read only =01)
Signaled Target Abort
Received Target Abort (Reserved =0)
Received Master Abort (Reserved =0)
Signaled System Error
Dected Parity Error
Bit 0-4
Bit 5
Bit 6
Bit 7
Reserved.
A logical 1 indicates a device is capable of running at 66 MHz. A logical 0 indicates 33 MHz.
This optional bit indicates that this device supports User Difinable Features.
This optional bit indicates whether or not the target is capable of accepting fast back-to-back transac-
tions when the transactions are not to the same agent.
Implemented by bus masters only.
These bits encode timing of DEVSEL#. There are three allowable timings for asserted of DEVESEL#
. They are encoded as binary value 00 for fast , 01 for medium , and 10 for slow .
This bit is set by TP6508 whenever its transaction is terminated with target-abort.
Implemented by bus masters only.
Implemented by bus masters only.
This bit must be set whenever the device asserts SERR#.
This bit must be set by the device whenever it detects a parity error, even if parity error handing is
disabled by bit 6 in the Command register.
Bit 8
Bit 9-10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Extended Index Register PREG Hex 08 : Revision ID Register
This is a read only register.
Default value after hardware reset is Hex 00.
Port address is Hex CFC.
D0-7
Revision ID bit 0 to 7
Bit 0-7
These bits specify TP6508 specific revision identifier. The bit 0 to 2 is as same as the
bit of Revision Code of Extended Reg. SREG 05.
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