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參數(shù)資料
| 型號(hào)： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁數(shù)： | 75/134頁 |
| 文件大小： | 600K |
| 代理商： | TP6508 |
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P.72
Bit 0-5
TP6508 has a internal line buffer to store pixel-data of a line for dual flat
panel device. Specially, the line buffer must work on the condition that TP6508
has turned on panel frame buffer and it do as a temp store of frame buffer.
These bits can be programmed to set the line buffer length which base on flat
panel horizontal resolution or do for simulation test only.
Reserved.
Bit 6-7
Extended Indexed Register CREG AC : Extended CRT Control Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3
D4
D5
D6-7 Reserved
Enable extended horizontal timing set
Enable extended vertical timing set
IBM CRT control registers lock
Half panel timing source selection
Text mode vertical expansion selection
Enable 24-bit TFT panel interface
Bit 0
A logical 1 forces TP6508 using the extended CRT horizontal timing set
the flat panel resolution for LCD or LCD-CRT display mode. A logical 0 set TP6508 working on
using the IBM CRT horizontal timing set registers.
A logical 0 set TP6508 working on using the IBM CRT vertical timing set registers . A logical 1
forces TP6508 using the extended CRT vertical timing set registers to match or fit the flat panel
resolution for LCD or LCD-CRT display mode. Then, we can use the MISCREG bit 6,7 to select the
extended vertical timing set register group. The more description is in CREG A5 bit-3 description.
MISCREG Bit-7,
Bit-6
Selected Vertical CRT register group
0
0
Reserved
0
1
Use the 400-line vertical timing CRT regs. CREG C7-CD
1
0
Use the 350-line vertical timing CRT regs. CREG C7-CD
1
1
Decided by CREG A5 bit-3
A logical 1 enables CRTC lock to protect the parameter of IBM CRT control register.
A logical 0 inducates TP6508 to generate the half panel timing by setting Ext. Reg. hex A5 for internal
panel controller use . A logical 1 forces TP6508 use the half of
the CRT Reg. hex 12.
A logical 0 selects to insert a line by counting every 3 or 5 lines for x350 or x400 resolution text
mode to fit the vertical resolution of flat panel . A logical 1 selects to insert 5 or 3 line into every
character for x350 or x400 resolution text mode to fit the vertical resolution of flat panel .
A logical 1 enables TP6508 to implement 24-bit panel interface for 18-bit or 24-bit TFT panel. A
logical 0 forces TP6508 to implement 16-bit panel interface for 9/12/15/16-bit panel.
Reserved
registers to match or fit
Bit 1
Bit 2
Bit 3
VDE signal as it by programming
Bit 4
Bit 5
Bit 6-7
Extended Indexed Register CREG AD : Extended CRT Horizontal Total Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0-7 Extended CRT horizontal total bit 0 to 7 (-5 )
Extended Indexed Register CREG AE : Extended CRT Horizontal Display Enable End
Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
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