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參數(shù)資料
| 型號： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁數(shù)： | 31/134頁 |
| 文件大?。?/td> | 600K |
| 代理商： | TP6508 |
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P.28
CRT FIFO (Display FIFO)
The CRT FIFO logic is the interface between display memory and the Graphics controller during
the CRT cycle. The Sequencer Controller takes an arbitration between CRT, CPU and Refresh cycle.
Because the CRT cycle has the highest priority, the Sequencer Controller can perform a vast fast-page
mode to fetch the display data and latch those data into the CRT FIFO. During display , the Graphics
Controller takes the display data from the CRT FIFO by the display sequence.
Two threshold registers is defined as a high and a low indicator of the CRT FIFO. These regis-
ters data are then compared with the number of available display data in the CRT FIFO. The compare
outputs are sent to the Sequencer Controller for arbitrating operation. When the contents in the CRT
FIFO are under the low threshold, the CRT FIFO issues a request to the Sequencer Controller for more
CRT cycles. When the contents in the CRT FIFO leaps over the high threshold or reaches full of the
FIFO, the CPU gains the highest priority. With this CRT FIFO logic, the TP6508 optimizes system
performance.
Attribute FIFO
The dynamic memory cycle allocation architecture is used in TP6508. Specially , in text mode
we integrate 12 levels attribute FIFO storing the attribute information latches the text attribute , ASCII
data and cursor state in order to improve performance.
The Attribute FIFO logic is the interface between display memory and CRT FIFO during the CRT
attribute-accessed cycle in text mode. Two threshold registers is defined as a high and a low indicator
of the Attribute FIFO, these registers data compare with the number of available text attribute data in
the Attribute FIFO. The content-data are sent to CRT FIFO for arbitrating operation. With the At-
tribute FIFO logic, the TP6508 optimizes system performance in text mode only .
Write Buffer
When the write buffer function is enabled, a system microprocessor writes to the Write Buffer
logic instead of writing directly to the display memory or accessing I/O-write command. A four-stage
buffer latches the address, data and other status and maintains a zero wait state write cycle to improve
the system performance. If the content of the buffer is not empty, the Write Buffer logic requests the
Sequencer Controller to insert a CPU cycle.
For compatibility issue, when the content of the buffer is not empty, the Sequencer Controller
holds attempts to read display memory and write I/O register until the TP6508 completes processing
all items in the Write Buffer logic.
Dual Frequency Synthesizer
The Dual frequency Synthesizer generates the memory clock (MCLK) and the display clock (VCLK)
from a single reference frequency - 14.318MHz . . The frequency of each clock is programmable by
setting divisor value in the extended regs. that contains field for PLL (Phase Lock Loop), VOC (Volt-
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