參數(shù)資料
型號(hào)： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁(yè)數(shù)： 21/134頁(yè)
文件大?。?/td> 600K
代理商： TP6508
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)
P17
* Display Memory Interface (82 pins)
Symble Type Drive Pin Number Active Function
AA9
AA[8:0]
I/O
I/O/U
4maR
4maR
CA[9:8]
CA[7:0]
MAD[15:0]
I/O
O
I/O/U
4maR
4maR
4maR
MBD[15:0]
I/O
4maR
MCD[15:0]
I/O
4maR
RASA*
O
4maR
RASB*
O
4maR
RASC*
I/O
4maR
CASAL*/WEAL*
O
4maR
CASAH*/CASA*
O
4maR
CASBL*/WEBL*
O
4maR
CASBH*/CASB*
O
4maR
CASCL*/WEAL*I/O
4maR
CASCH*/CASC*
I/O
4maR
WEA*/WEAH*
O
4maR
WEB*/WEBH*
O
4maR
WEC*/WECH*
O
4maR
OEAB*
O
8maR
OEC*
I/O
4maR
True
True
True
True
True
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Display memory address bit 9 to 0 for DRAMs
A and B. A pull-high mechanism gives a default
high value in those configuration data.
Display memory address bit 9 to 0 for DRAMs
C.
These pins are used to transfer data between the
TP6508 and display memory, DRAM A. A pull-
high mechanism gives a default high value in
those configuration data.
These pins are used to transfer data between the
TP6508 and display memory, DRAM B.
These pins are used to transfer data between the
TP6508 and frame buffer memory, DRAM C.
When a frame buffer DRAM isn't requireed, this
bus may optionall be used to input up to 24 bits
of RGB data from the external PC-Video
subsystem(device).
Row address strobe for latching 10-bit row ad-
dress signal into display memory, DRAM A..
Row address strobe for latching 10-bit row ad-
dress signal into display memory, DRAM B..
Row address strobe for latching 10-bit row ad-
dress signal into display memory, DRAM C..
Column address strobe for DRAM A lower byte
in dual-CAS application. In dual-WE applica-
tion, it is used as write enable signal for DRAM
A lower byte.
Column address strobe for DRAM A upper
bytein dual-CAS application.
Column address strobe for DRAM B lower
bytein dual-CAS application.
Column address strobe for DRAM B upper
byte.in dual-CAS application.
Column address strobe for DRAM C lower
bytein dual-CAS application.
Column address strobe for DRAM C upper
bytein dual-CAS application.
Write enable signal for DRAM A in dual-CAS
application. In dual-WE application, it is used
as write enable signal for DRAM A upper byte.
Write enable signal for DRAM Bin dual-CAS
application.
Write enable signal for DRAM Cin dual-CAS
application.
Data output enable signal for DRAM A and
DRAM B.
Data output enable signal for DRAM C.
154,153,152,151,150,
149,148,147,146,145
99,98,97,96,95,
94,93,92,91,90
177,176,175,174,173,
172,171,170,169,168,
167,166,165,164,163
162
144,143,141,140,138,
137,136,135,134,133,
132,131,130,129,128,
127
122,121,120,119,118,
117,116,115,114,113,
112,111,110,109,107,
106
156
123
101
160
159
126
125
104
103
157
124
102
155
100
相關(guān)PDF資料
PDF描述
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TP7S8 TRANSISTOR | BJT | NPN | 80V V(BR)CEO | 7A I(C) | TO-220VAR
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