P.57
D3
D4
D5
D6
D7
Enable IO 16 bit access
VGA subsystem enable port address set to Hex46E8(default 3C3)
Select VGA subsystem power-on in enable state
Enable ISA bus width 8 bit
Select SA address decoder
(These bits are latched from MAD0 to MAD7 at power on reset.)
Bit 0
When bus interface was selected VESA/CPU direct local bus connection , then this can set to logical 1 to
enable BIOS ROMCS* signal output from OFF/EPROM* pin(pin 178).
We can set this bit to logical 0 to enable TP6508 BIOS decoding to expansion to 64 kb address do-
main.
When previous bit was set to logical 1, then this bit can be setting to relocate
VGA BIOS decoding address.
Bit 2
Decoding address
0
Hex E0000 to EFFFF
1
Hex C0000 to CFFFF
A logical 0 enables TP6508 IO 16 bit access.
This bit selects the address of the video subsystem enable bit location. A logical 0 indicates the ad-
dress of the video subsystem bit is Hex 46E8 , a logical 1 indicates that it is located on the address
Hex 3C3.
A logical 0 indicates TP6508 power-on in the enable state that allows memory and IO accessing . A
logical 1 indicates TP6508 in the disable state at power-on.
A logical 0 forces TP6508 connects to 8 bit width host bus .
A logical 1 forces TP6508 connects to
16 bit width host bus.
A logical 1 indicates TP6508 use ALE signal to latch LA address signal . A logical 0 indicates
TP6508 directs to decode SA address by bus command signals (MEMW*,MEMR*,IOW*,IOR*) .
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Extended Indexed Register SREG CF: Configuration Register 2
This is a read only register.
Port address is Hex 3C5.
Default value after hardware reset is Hex FF. (Chip internal pull high during power on reset)
D0-2 TP6508 into Test mode selection bit (Latched from MD 4 to 5)
D3
Reserved
D4-7 Display type selection bits
(These bits are latched from MAD8 to MAD15 at power on reset.)
Bit 0-2
These bit is used to enable TP6508 into test mode for the internal analog device blocks, including of
the dual frequency synthesizer and RAMDAC . We can directly access the internal analog device
blocks by TP6508's I/O pins.
Bit 2
Bit 1
Bit 0
Test device
1
1
0
MCLK analog device function test mode
1
0
1
VCLK analog device function test mode
0
1
1
DAC analog device function test mode
Reserved.
These bits are used to read back for VGA BIOS setting display type .
Bit-7
Bit-6
Bit-5
Bit-4
Display Type
0
0
0
0
NTSC TV
0
0
0
1
LCD/NTSC TV
0
0
1
0
800x600 color TFT
0
0
1
1
800x600 color DSTN
0
1
0
0
CRT-like TFT
0
1
0
1
Dual-scan STN LCD
0
1
1
0
800x600 color TFT
Bit 3
Bit 4-7