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參數(shù)資料
| 型號(hào)： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁(yè)數(shù)： | 64/134頁(yè) |
| 文件大小： | 600K |
| 代理商： | TP6508 |
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P.61
Bit 3
Bit 4
If previous bit =1 , then programming this bit would set the output state of FPVCC.
If bit2 =1 , then programming this bit would set the output state of panel control signal
(FPVDCLK,MOD,LFS,LLCLK,DE*) and panel data bus. A logical 0 forces TP6508 set these output
to logical 0 . A logical 1 indicates these signals output normal .
If bit2 =1 , then programming this bit would set the output state of FPVEE.
The bit is used to enable the panel control state machine into test mode (short the power sequency
cycle time) . It is to be enable for internal test only.
A logical 0 enables TP6508 output FPVEE signal from Pin 61. A logical 1 enablesTP6508 output
FPBACK signal from Pin 61.
Bit 5
Bit 6
Bit 7
Extended Indexed Register SREG D7 : Memory mapping I/O Offset Low Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-7 Graphics engine memory mapping I/O command offset bit 0 to 7
Bit 0-7
When memory map I/O was enabled (SREG bit-3=1), these bits would use to do as the segment ad-
dress of I/O command for replacing the address A16 to A23. We can set these bits to relocate the I/
O port address of Graphics Engine registers. By memory map I/O addressing, these registers are
accessed
as
memory
command
and
ZZZZ,ZZZZ,ZZZZ,xxxx,xxYY,YYYY,YY00. The address value - 'Z..' is determined by this register
and SREG D8. The low address value - 'Y..' is determined by SREG F0. The address value - 'x..' is
determined by the Graphics Engine control register indexed value. Then TP6508 can access these
registers with 16-bit data width by decoding at them, being conjunction with 'Y..' and 'x..' , directly.
located
at
memory
address
binary
Extended Indexed Register SREG D8 : Memory mapping I/O Offset High Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-3 Graphics engine memory mapping I/O command offset bit 8 to 11
D4-7 Reserved
Bit 0-7
When memory map I/O was enabled, these bits would use to do as the segment address
of I/O command for replacing the address A24 to A27.
Extended Indexed Register SREG D9 : PC Video Control Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3-7 Reserved
Enable PC Video interface
Select PC Video width
Enable PC Video color key
Bit 0
A logical 1 enables PC video interface on DRAM-C pins that includes of RASC* ,CASCH* ,CASCL*
,WEC* , MCD[15:0]. A logical 0 disables it.
When previous bit is set to logical 1, this bit is used to select the PC video interface width. A logical
0 forces TP6508 inplements a 18-bit width PC video interface. A logical 1 enables TP6508 inplements
a 24-bit width PC video interface and sets OEC*,AA9,FPBACK,ACTI as video input. When this bit is
set to logical 1, a 24-bit panel interface is also avilable by CA[7:0] being becomed P[23:16]. Spe-
cially, this bit shouldn't be set to 1 if the SREG D0 bit-6 is set to 1.
Bit 1
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