參數(shù)資料
型號： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁數(shù)： 54/134頁
文件大小： 600K
代理商： TP6508
P.51
Extended Sequencer Register Description
The following registers are TP6508 extended sequencer registers. These registers
are accessed by first writing the index of the desired register to the Sequencer Index register,
i.e. address Hex 3C4 and then accessing the register using the address Hex 3C5. These regis-
ters are protected by password/Identification register (Extended Index Register Hex 05) .
Extended Indexed Register SREG C0: VGA Control Register
This is a read/write register.
Default value after hardware reset is Hex 00.
Port address is Hex 3C5.
D0
D1
D2
D3
D4
D5
D6
D7
Enable CPU write buffer
Disable VGA palette snooping for VESA local bus
Enable linear addressing
Enable memory map I/O
Enable Graphics engine read/write
Graphics engine active enable
Enable VAFC interface
Enable VAFC PCLK output divided by 2
Bit 0
TP6508 support CPU write buffer to improve the performance when CPU writes a data into video
memory . A logical 1 enables this function, a logical 0 disables it.
A logical 0 enables TP6508 snoops VGA palette write for VESA local bus . A logical 0 disables it.
IBM compatible display address uses low base 1M address bit 0 to 19 and locates at Hex A0000 to
AFFFF or Hex B0000 to BFFFF . A logical 1 enables TP6508 to remape display memory in continu-
ously linear address at over the base 1M-byte
address . A logical 0 disables it and forces TP6508
in bank memory addressing on
enhanced display mode.
By base addressing, we can used the reg. SREG F0 and SREG F1 to assign the base low address . (See
the reg. description of SREG F0 and SREG F1) Then TP6508 can access these registers with 16-bit
data width by decoding at them, being conjunction with 'x..' and 'Y..' , directly. By memory map I/O
addressing forces TP6508 uses memory command accessing to access I/O command and remapes I/O
command address on where are determined by Memory Mapping I/O Command offset Register ( See
the reg. description of SREG D8).
Bit 3
Addressing mode
0
Base Addressing
1
Memory I/O Addressing
A logical 1 enables to access the Graphics Engine Control registers.
A logical 1 enables TP6508's Graphics Engine in operated mode. A logical 0 disables it .
A logical 1 enables TP6508 implement VAFC interface.
A logical 1 forces TP6508 output PCLK frequency divide by two for VAFC.
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Extended Indexed Register SREG C1 : Extended mode select Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3
D4
Enhanced 16 color mode enable
Enhanced 256 color mode enable
Enable 32k super-colors mode
Enable 64k super-colors mode
Enhanced 16.8M color enable
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