P19
SHFCLK(CL2)
O
12maR
LP(CL1)
PHSYNC
DE
OT
8maR
FLM
PVSYNC
OT
8maR
M
DE
O
8maR
P[23:16]
P[15:0]
O
O
4maR
8maR
SLD[7:0]
O
8maR
SUD[7:0]
O
8maR
LD[3:0]/ED[3:0]
O
8maR
UD[3:0]/OD[3:0]
O
8maR
70
68
67
69
97,96,95,94,93,
92,91,90
88,87,86,85,84,
83,82,81,79,78,
76,75,74,73,72,71
75,76,78,79,85,
86,87,88
71,72,73,74,81,
82,83,84
75,76,78,79
71,72,73,74
True
High
True
High
High
True
True
High
True
True
True
True
True
True
True
This signal is used to driver the flat panel shift
clock .
This signal is used to drive the flat panel line
clock for LCD panels or the horizontal sync for
PLASMA/EL panels and some TFT panels. It
can also do as the display enable signal (DE)
for flat panel.
This signal is used to start a new frame on flat
panels for LCD panels or the vertical sync for
PLASMA/EL panels and some TFT panels.
This signal is used to provide the AC inversion
for flat panels to prevent a chemical damage. It
can also do as the display enable signal (DE)
for flat panel.
These signals contain RED/GREEN/BLUE color
data for 9/12/18/24 bit interface TFT-color LCD
panels.
These signals contain the lower data for color
STN LCD panels .
These signals contain the upper data for color
STN LCD panels .
These signals contain the lower data for gray
dual-scan LCD panels .
These signals contain the even data for gray
PLASMA/EL panels .
These signals contain the upper data for gray
dual-scan LCD panels .
These signals contain the odd data for gray
PLASMA/EL panels .
* Power Management Pins (5 pins)
53
62
61
54
178
High
High
High
Low
High
The ACTI output is an active high signal that is
driven high every time a valid VGA access
(memory or I/O read/write).
This signal is part of the flat panel power-down
sequencing and should be connected to the flat
panel LOGIC power enable . ( default = 0 after
reset-on)
This signal is part of the flat panel power-down
sequencing and should be connected to the flat
panel BIAS power enable . ( default = 0 )
This signal is part of the flat panel power-down
sequencing and should be connected to the flat
panel BACKLIGH enable . ( default = 1 )
This input is used to force TP6508 into Off
mode enable . This pin can also redefined as an
output to indicate the active status . It may be
also configed as other function- by extended
register.
ACTI
I
(I/O)
-
FPVCC
O
8maR
FPVEE
O
8maR
FPBACK
O
8maR
OFF
I/O
4maR
Symble Type Drive Pin Number Active Function
* Flat Panel Interface (28 pins)