P15
V. Pin Descriptions
SD[15:0]
I/O
8maR
SA[16:2]
SA[1:0]
I (I/O)
I
-
LA[23:22]
A21
A20
LA[19:17]
AEN
I
I (I/O)
I
I (I/O)
I
(I/O)
-
-
ALE
I
-
SBHE*
I
-
IORD*
I
(I/O)
I
(I/O)
-
IOWR*
-
MEMR*
I
-
MEMW*
I
-
IORDY*
OT
12maR
IOCS16*
OT
(I/O)
12maR
MEMCS16*
OT
(I/O)
I/S
12maR
RESET*
-
IRQ
OT
(I/O)
I
8maR
REF*
-
OWS*
OT
(I/O)
8maR
33,34,35,36,37
38,40,41,44,45
46,47,48,49,50,51
195,194,193,192,191,
190,189,188,187,186,
185,183,182,180,179,
21,43
28,201,200,199,198,
197,196
31
22
32
27
25
11
23
24
18
19
207
30
10
20
True
True
True
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
These signals provide 16 data bits transfer on
ISA bus with system microprocessor.
Address Bit 16 Through 0 are used to
address frame buffer and I/O ports with TP6508.
Address Bit 23 Through 17 are used to
address frame buffer and I/O ports with TP6508.
In general ,these signals are not gated address
LA[19:17]
A high active signal used to detect the TP6508
from the I/O channel to avoid a disturbance from
the DMA controller.
This signal is used to latch those ungated ad-
dress bus.
It indicates and enables transfer of data on the
high byte of data bus and is used with A0 to dis-
tinguish between high and low byte.
I/O read signal comes from a host micropro-
cessor to read data from TP6508 control.
I/O write signal comes from a host micropro-
cessor to read data from TP6508 control regis-
ters.
Memory read signal comes from a host
microprocessor to read data from video
memory.
Memory write signal comes from a host
microprocessor to read data from video
memory.
This signal is driven low by TP6508 to lengthen
the memory or I/O accessed cycle.
This signal is driven low to indicate that the
TP6508 can execute an I/O operation at the ad-
dress currently on the 16-bit bus mode.
This signal drives a 16-bit memory cycle for
16-bit bus data transfer.
This pin is connected to the signal that was in-
verted from the system board to reset the
TP6508.
The vertical retrace interrupt.
This signal is driven by system mother board
logic and is used to indicate a memory
refresh cycle is in operation.
This signal is driven by TP6508 to short the
memory accessed cycle for improving system
performance.
* ISA Bus Interface (54 pins)
Symble Type Drive Pin Number Active Function