參數(shù)資料
型號： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁數(shù)： 83/134頁
文件大?。?/td> 600K
代理商： TP6508
P.80
PCI Local Bus Configuration Register Description
The following registers are TP6508 PCI local bus configuration registers. These registers
are accessed by first writing the index of the desired register to the Index register, i.e. address
Hex CF8 and then accessing the register using the address Hex CFC. Read accesses to reserved
(index Hex 0C,0D,0F,18,1C,20,24,28,2C,30,34,38,3E,3F) or unimplemented (index Hex 40 to
FF) register can be completed normally and a data value of 0 returned.
Extended Index Register PREG Hex 00 : Vendor ID Register
This is a read only register.
Default value after hardware reset is Hex 10D4.
Port address is Hex CFC.
D0-15
Vendor ID bit 0 to 15
Bit 0-15
This field identifies the manufacturer of the device.
Extended Index Register PREG Hex 02 : Device ID Register
This is a read only register.
Default value after hardware reset is Hex 860B.
Port address is Hex CFC.
D0-15
Device ID bit 0 to 15
Bit 0-15
This field identifies the particular device. The bit 0 to 4 is as same as the bit of
Identification Code in Extended Reg. SREG 05.
Extended Index Register PREG Hex 04 : Command Register
This is a read/write register.
Default value after hardware reset is Hex 0000.
Port address is Hex CFC.
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10-15
IO space
Memory space
Bus Master (Reserved =0)
Special cycle (Reserved =0)
Memory write and invalidate (Reserved =0)
VGA palette snoop
PERR# enable
Wait cycle control (Reserved =0)
SERR# enable
Fast Back-to-Back Enable (Reserved =0)
Reserved =0
Bit 0
Controls TP6508 response to I/O space accesses . A logical 0 disables the device response. A logical
1 allows the device to respond to I/O space accesses .
Controls TP6508 response to memory space accesses . A logical 0 disables the device response. A
logical 1 allows the device to respond to memory space accesses .
Implemented by bus masters only. Controls a device's ability to act as a master on PCI bus. A logical
1 allows the device to behave as a bus master . A logical 0 disables it .
Controls a device's action on special cycle operation .
This is an enable bit for using the Memory Write and Invalidate command .
Bit 1
Bit 2
Bit 3
Bit 4
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