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參數(shù)資料
| 型號： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁數(shù)： | 55/134頁 |
| 文件大?。?/td> | 600K |
| 代理商： | TP6508 |
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P.52
D5
D6
D7
Enable 132 column text mode
Enable interlace display
Enable bank memory addressing on enhanced 16-color display
Bit 0
Bit 1
Bit 2
A logical 1 directs the TP6508 to work in the enhanced 16 color mode.
A logical 1 forces the TP6508 to display the 256 color except the Mode 13.
When bit-1 was set to logical 1, we can force the build-in internal RAMDAC to
support Hicolor-15
TM
compatible display mode architecture by setting this bit to logical 1.
When bit-1 was set to logical 1, we can force the build-in internal RAMDAC to
support Hicolor-16
TM
compatible display mode architecture by setting this bit to logical 1.
When bit-1 was set to logical 1, we can force the build-in internal RAMDAC to
support Hicolor-24
TM
compatible color display mode architecture by setting this bit to logical 1.
A logical 1 directs the TP6508 to display 132 columns text mode.
A logical 0 directs the TP6508 to perform a non-interlaced display mode. A logical 1
enables a interlaced display mode to fit the synchronous frequency of the monitor.
A logical 1 directs TP6508 to display enhanced 16-color mode by bank memory
addressing. A logical 0 directs TP6508 to display enhanced 16-color mode by
location continuous 128K-byte memory at A0000 to BFFFF.
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Extended Indexed Register SREG C2: Clock Select Register
This is a read/write register.
Default value after hardware reset is Hex 00.
Port address is Hex 3C5.
D0-1 Extended clock select bit 0 to 1
D2-3 Reserved
D4
Enable extended clock select bit 0 and bit 1
D5
ACTI statue/data
D6
ACTI Pin(pin 53) output control
D7
Select 16.8M color mode in four-byte architecture
Bit 0-1
When the bit-4 was set to logical 1, these two bits replace the MISCREG bit 2-3. The
bit-0 or MISCREG bit-2 is used to select the internal VCLK clock synthesizer
programming regs. set for deciding video clock frequency.
MISCREG bit-2 or SREG C2 bit-0
0 :
1 :
Reserved.
A logical 1 directs previous two bits as the video clock select signals. A logical 0
inhibits the function of extended clock select bit 0 and 1.
This bit is reflected the ACTI pin status. When ACTI is redefined as user control
output that is configured by bit 1, this bit determins the data output on ACTI pin.
When SREG D0 bit 6=1,SREG D9 bit 1-0=11, this bit can select ACTI Pin(pin 53) output function
as following:
Bit 6
ACTI Pin Function
0
ACTI output. ACTI responces high during vaild VGA access operations.
1
User control output. Output data from SREG C2 bit 5.
Ture color(16.8M color) display mode memory access architecture selection:
Bit 7
16.8M color mode architecture selection
0
In three-byte memory architecture.
1
In four-byte memory architecture..
Selected Regs. group
Use the SREG C3,C5
Use the SREG C4,C6
Bit 2-3
Bit 4
Bit 5
Bit 6
Bit 7
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