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參數(shù)資料
| 型號(hào)： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁(yè)數(shù)： | 58/134頁(yè) |
| 文件大小： | 600K |
| 代理商： | TP6508 |
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P.55
Bit 0-7
This register,in conjunction with MCLK Numerator Value Register, is used to
determine the frequency of memory clock.
Extended Indexed Register SREG CB: Clock Generator Test Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-1 MCLK/VCLK signal output from OFF pin enable
D2-3 VCLK generated selection Select MCLK as VCLK source
D4
Enable pixel clock divide by two for TV display
D5
MCLK frequency synthesizer off enable
D6
VCLK frequency synthesizer off enable
D7
Oscillator off enable
Bit 0-1
These bits are used to select MCLK/VCLK signal output from OFF pin.
Bit 1
Bit 0
Output signal from OFF pin
0
0
Other signal
0
1
Internal MCLK signal
1
X
Internal VCLK signal
These bits are used to select VCLK clock source .
Bit 3
Bit 2
VCLK generated selection
0
0
From VCLK frequency synthesizer
0
1
MCLK synthesizer output dividing by 2 as the VCLK
1
0
VCLK synthesizer output dividing by 2 as the VCLK
1
1
From MCLK frequency synthesizer
A logical 1 forces TP6508 video clock frequency divide by two to generated the
signal for TV display .
A logical 1 forces TP6508 to power off MCLK frequency synthesizer.
A logical 1 forces TP6508 to power off VCLK frequency synthesizer.
A logical 1 forces TP6508 to power off Oscillator.
Bit 2-3
Bit 4
composite sync.
Bit 5
Bit 6
Bit 7
Extended Indexed Register SREG CC: MISC. Control Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3
D4-5 Host bus memory access data bus select
D6
Emulation 16-bit access disable for 16 color display modes
D7
Bypass internal pallete enable
DAC monitor senser off enable
DAC off enable
Synchronous reset timing generator
VGA palette off enable
Bit 0
Bit 1
Bit 2
A logical 1 forces TP6508 to power off Monitor Sense logical block.
A logical 1 forces TP6508 to power off DAC block and disable CRT display refresh.
When logical 1 we can used this bit to reset TP6508 timing generator and synchronize the internal
state machine.
A logical 1 forces TP6508 VGA palette power off.
These bits are used to set the host bus memory access data width.
Bit 3
Bit 4-5
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