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參數(shù)資料
| 型號(hào)： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁(yè)數(shù)： | 63/134頁(yè) |
| 文件大?。?/td> | 600K |
| 代理商： | TP6508 |
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P.60
D5
D6-7 Reserved
Enable Keyboard activity to reset standby/off timer
Bit 0
Bit 1
Bit 2-3
Bit 4
Bit 5
Bit 6-7
A logical 1 enables TP6508 to reset backlight timer for flat panel by VGA access.
A logical 1 enables TP6508 to reset backlight timer for flat panel by keyboard activity.
Reserved
A logical 1 enables TP6508 to reset standby timer for flat panel by VGA access.
A logical 1 enables TP6508 to reset standby timer for flat panel by keyboard activity.
Reserved
Extended Indexed Register SREG D5 : OFF Timer and Slow Refresh Register
This is a read only register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-3 Timer for off control bit 0 to 3 (Unit : 4 minute error -1/4 minute)
D4
Enable slow refresh in off mode
D5-6 Slow refresh rate selection bit 0 to 1
D7
Select external 32kHz clock as power management clock base
Bit 0-3
These bits are used to program the time that active mode go into off mode after the system was in the
rest state.
A logical 1 enables TP6508 to slow down the refresh rate that specifies by next two bits in the off
mode.
When TP6508 goes into off mode , it provide programmable refresh rate for power
saving .
Bit 6
Bit 5
Refresh rate (KHz)
0
0
No refresh
0
1
32
1
0
16
1
1
8
User can use this bit to select the power management clock source. A logical 0 TP6508 selects the
internal refresh clock base being divided the frequency of 14.318MHz clock source . And a logical
1 TP6508 switches the clock source to external 32KHz clock input.
Bit 4
Bit 5-6
Bit 7
Extended Indexed Register SREG D6 : Override and Status control Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3
D4
D5
D6
D7
FPBACK output override
FPBACK polarity
FPVCC/FPSIG/FPVEE output override
FPVCC status
FPSIG output status
FPVEE output status
Panel control state machine test mode enable
FPVEE Pin(pin 61) output control
Bit 0
Bit 1
A logical 1 indicates TP6508 would override FPBACK standby mode.
If previous bit =1, then programming this bit would set the output state of FPBACK. If previous bit
=0, then bit is used to invert the FPBACK output polarity.
A logical 1 indicates TP6508 would override FPVCC standby mode .
Bit 2
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