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| 型號(hào)： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁(yè)數(shù)： | 30/134頁(yè) |
| 文件大小： | 600K |
| 代理商： | TP6508 |
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P.27
It provides a linear memory address logic and a raster address logic to produce memory address
signals for fetching display informations from VGA frame memory.
Attribute Controller (ATC)
The Attribute Controller provides flexible high-speed display shifting and attribute processing.
It is designed for both text and graphics VGA display applications.
In text modes, the Attribute Controller takes in eight bits of character code data and eight bits of
attribute data via the Graphics Controller. The character code is used to lookup into a character font
table that is located in the Map3 of the display memory. The character font data is loaded into a
parallel-to-serial shift register. The serial output from the shift register is used to select a foreground
or a background color that is assigned in the attribute data byte. Text blinking, underline and cursor are
also the responsibility of the Attribute Controller.
In graphic mode, the display data are converted into pixel color data in groups of 16, 8, 2,or 1
adjacent bits, passed through an internal color palette table, and sent out serially to the RAMDAC. In
the 256-color mode, the display data is latched twice to form an 8-bit pixel data.
Graphics Controller (GFXC)
The Graphics Controller is the interface between CRT FIFO and both the Attribute Controller
during active display and the system microprocessor during display memory reads or writes.
During display, memory data is latched from CRT FIFO and sent to the Attribute Controller. In
graphic mode, the parallel memory data is converted to serial bit-plane data before being sent out. In
text mode, the parallel attribute data is sent to Attribute Controller directly.
During a system microprocessor writes or reads to display memory, the graphics controller can
perform logical operations on the memory data before it reaches display memory or the system micro-
processor data bus, respectively. These logical operations consisted of four logical write modes and
two logical read modes.
Address Multiplexer (AMUX)
The Address Multiplexer controls the address bus that is sent to the display memory. It includes
RAS* , CAS* , WE* , and OE* timing. During the CRT cycle it sent the display memory address that
comes from CRT Controller to the display memory for fetching the display information. When a system
microprocessor writes or reads the display memory, the Address Multiplexer connects the system
microprocessor address bus to the display memory.
When the write buffer function is enabled, a system microprocessor write operation is done first
to the Write Buffer logic, then the system address and data signals are latched in the logic. The
Sequencer Controller inserts a CPU cycle to perform a write operation by a request coming from Write
Buffer logic. At this time, the Address Multiplexer logic connects the address latched by Write Buffer
to display memory.
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