參數(shù)資料
型號： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁數(shù)： 51/134頁
文件大小： 600K
代理商： TP6508
P.48
Backward Compatible Register Description
The following registers are TP6508 backward compatible registers. These registers are
accessed by first writing the index of the desired register to the Sequencer Index register, i.e.
address Hex 3C4 and then accessing the register using the address Hex 3C5. Specially , these are
not protected by password/Identification register (Extended Index Register Hex 05) .
Extended Indexed Register CREG 05 : Password/Identification Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
Write operation (=> Hex 86) :
D0-7
Password
Read operation (=> Hex 0B for correct password or Hex F4 for incorrect passward):
D0-4
Identification Code
D5-7
Chip Version Code
With the password register, the TP6508 protects the extended register to avoid incorrectly application program-
ming. When user wants to access the extended registers, he must first write Hex 86 to this register to unlock the
protection. When user reads the content of this register, he can get a value of Hex 0B that is used to distinguish the
TP6508. To enable the protection operation by writing other values into the register , and you can read back a value of
Hex F4.
Extended Indexed Register SREG 06 : Extended Memory Bank MISC. Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3-7 Reserved
Enable Bank C and Bank D
Disable dual Bank (window) operation for Bank C and D
Enable read/write bank operation
Bit 0
For compatibility with the HM86305 that has only three bit bank select for up to
512K- byte display memory, a logical 0 directs the bank selection from Bank A ,
Bank B or both. When this bit is set to a logical 1, the TP6508 enables both Bank C
&
D and Bank A & B.
Refer the SREG 09 bit 0-5 description. This bit is used to select the BANK D location
address from hex. A0000 to hex. AFFFF or from Hex B0000 to Hex BFFFF . A logical
0 selects BANK D addressing in hex. B0000 to hex. BFFFF.
A logical 1 forces BANK C in write access operation and BANK D in read access operation only.
Bank C & D are both location at address hex. A0000 to AFFFF . A logical 0 doesn't enable it.
Bit-2
Bit-1
Bit-0
Memory bank & segment selection
0
0
0
BANK A&B R/W access by segment address A000&B000
0
0
1
BANK C&D R/W access by segment address A000&B000
0
1
0
BANK A R/W access by segment address A000 only
0
1
1
BANK C R/W access by segment address A000 only
1
X
X
BANK C Write access & BANK D Read access
by segment address A000
Reserved.
Bit 1
Bit 2
Bit 3-7
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