P.32
through GEC with the different color as the "Transparency Color Register" can not be modi-
fied if 'transparency polarity' bit is "1" .
In addition , there is a "Transparency Mask Registers" . If the mask bit is "1" , then the
color bit of destination pixel is not used in color compare and passes through . These is a
example in enhanced 256 color mode . If "Transparency color Registers" is written hex 36
and "Transparency Mask Registers" is written hex 28 and 'transparency polarity' bit is "0" ,
the destination pixels with color 16h , 36h , 1Eh or 3Eh would not be modified .
Command FIFO
When the Graphics Engine is in operation , we will transfer the necessary parameters ( X/Y
direction ,source/destination select, major movement , foreground/background color, ... etc..) to TP6508
by through the Command FIFO and write a graphics accelerate function command (Bit block transfer ,
Color expansion , Line drawing , ... etc..) in the last.
A eight-stage FIFO latches the command data including of graphics accelerate function command
and it's parameters and maintains a zero wait state write cycle to improve the system performance. If
the content of the FIFO is full , the Command FIFO logic requests the Sequencer Controller to assert the
wait cycle until to the FIFO isn't full. A better recommendation was to monitor the 'Graphics Command
Status Register' in the group of Graphics Engine Control Register before you write graphics engine
command to TP6508.
Hardware Cursor Controller
The Hardware cursor controller supports a 32x32 or 64x64 hardware cursor in 256-color,32k/
64k-color and 16.8M-color graphics mode. It supports the two-bit plane cursor data structure which
provides two colors plus Transparent and Inverted background color by following the Microsoft Win-
dows driver interface specification. In addition, a Auxiliary Color data function can replace the In-
verted background color function optionally . The pattern's data format of any pixel (two-bit) is :
Data bit-1
0
0
1
1
Data bit-0
0
1
0
1
Definition
Hardware cursor Primary color
Hardware cursor Secondary color
Transparent
Inversion or hardware cursor auxiliary color
(decided by GAREG 2A bit-15 selection)
Usually , the cursor pattern is stored in the off-screen display memory . The structure of cursor
pattern is 16-bytes by 64-line . All the 16-bytes join together from low address to high address and
from LSb to MSb to form a 64x2-bit bit-string . The screen display order of cursor pattern from left to
right is mapped to bit string from LSb to MSb per two-bits . To write the cursor pattern to display
memory can use Image Write or VGA memory write access directly . The cursor pattern start must
address at boundary of double-word .
Hardware cursor screen position, type, color selection, and pattern address of the cursor are to
be controlled by programming these registers in the group of Graphics engine control registers. The
hardware cursor data are allowed of multiple patterns to be storied in display memory and rapidly to
be selected one of the patterns as the active cursor's pattern by application program.