參數(shù)資料
型號(hào)： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁數(shù)： 57/134頁
文件大?。?/td> 600K
代理商： TP6508
P.54
Bit 0-7
This register,in conjunction with VCLK0 Numerator Value Register, is used to
determine the frequency of video clock.
Extended Indexed Register SREG C7 : CRT FIFO Threshold Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-3 CRT FIFO threshold high bit 0 to 2 (default = 0, point to actual value 4)
D4-7 CRT FIFO threshold low bit 0 to 2 (default = 0, point to actual value 3)
Bit 0-3
In the TP6508, memory cycle allocation is dynamic. When FIFO accumulated data is larger than FIFO
threshold high value, CPU cycle can occur without any wait state.
When CPU access video memory, it must depend on remainder data of CRT FIFO . When the number
of CRT FIFO data is less than the FIFO threshold low value, the only one thing can do is CRT access.
Threshold value affects the performance of TP6508.
Bit 4-7
Extended Indexed Register SREG C8 : Attribute FIFO Threshold Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-2 Attribute FIFO threshold bit 0 to 2 (default = 0, point to actual value 1)
D3-7 Reserved
Bit 0-2
This dynamic memory cycle allocation architecture is used in TP6508 .
we integrate the Attribute FIFO storing attribute data in order to improve performance in text mode.
Reserved
Specially, in text mode
Bit 3-7
Extended Indexed Register SREG C9 : MCLK Numerator Value Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex A1.
D0-6 MCLK numerator bit 0 to 6
D7
MCLK oscillation divider
Bit 0-6
This register,in conjunction with MCLK Denominator and Post Scalar Value Register, is used to de-
termine the frequency of video clock. These 7 bits numerator (N), 7 bits denominator (D), and 1 bit
post scalar (P) for clock (MCLK) determines its frequency according to the following expression:
OSC x [N+1] x [2P+2]
MCLK(MHz) =
[D+1]
This bit is used to divide the internal generated oscillation frequency. A logical 0 indicates to do it
divided by two. A logical 1 indicates to do it divided by four . Normally, we set to logical 1 when
MCLK outputs frequency lower 50MHz.
, OSC= 14.318 (MHz)
Bit 7
Extended Indexed Register SREG CA : MCLK Denominator and Post Scalar Value
Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 4D.
D0
D1-7 MCLK denominator bit 0 to 6
MCLK post scalar
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