參數(shù)資料
型號: SPD6729QCE
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: PCMCIA BUS CONTROLLER, PQFP208
封裝: MQFP-208
文件頁數(shù): 87/116頁
文件大?。?/td> 1442K
代理商: SPD6729QCE
PD6729 — PCI-to-PC Card (PCMCIA) Controller
72
Datasheet
Bit 7: FIFO Status / Flush FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is set to a ‘1’ during write
operations, all data in the FIFO is lost. During read operations, when this bit is a ‘1’, the FIFO is
empty. During read operations when this bit is a ‘0’, the FIFO has valid data.
This bit is used to ensure the FIFO is empty before changing any registers; registers should not be
modified while the write FIFO is not empty.
FIFO contents will be lost whenever any of the following occur:
RST# pin ( Table 1) is a ‘0’.
The card is removed.
VCC Power bit (see “Bit 4: VCC Power” on page 52) is programmed to a ‘0’.
10.3
Misc Control 2
Bit 0: External Clock Enable
This bit determines whether the external clock option is enabled. When set to a ‘1’, a clock
supplied to IRQ14/EXT_CLK will be internally divided by two and used as the internal clock for
the socket interfaces. This feature facilitates PCMCIA transfer cycles when the PCI bus clock is
stopped to conserve power. When set to a ‘0’, the PCI_CLK input is divided by two and used as the
internal clock, which drives the socket interfaces and specifies their timing.
Value
I/O Read
I/O Write
0
FIFO not empty
No operation occurs (default at reset)
1
FIFO empty
Flush the FIFO
Register Name: Misc Control 2
Index: 1Eh
Register Per: chip
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQ15/
RI_OUT*
Is RI Out
Reserved
5V Core
Suspend
Mode
Low-Power
Dynamic
Mode
External
Clock Enable
RW:0
RW:00
RW:0
RW:1
RW:0
0
External clock is disabled; clocking of socket interfaces provided by PCI_CLK
1
IRQ14/EXT_CLK pin will be used as an external clock input to provide clocking of socket
interfaces.
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