參數(shù)資料
型號(hào): SPD6729QCE
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: PCMCIA BUS CONTROLLER, PQFP208
封裝: MQFP-208
文件頁(yè)數(shù): 4/116頁(yè)
文件大?。?/td> 1442K
代理商: SPD6729QCE
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PCI-to-PC Card (PCMCIA) Controller — PD6729
Datasheet
101
13.3.3
PCMCIA Bus Timing Calculations
Calculations for minimum PCMCIA cycle Setup, Command, and Recovery timings are made by
first calculating factors derived from the applicable timer set’s timing registers and then by
applying the factor to an equation relating it to the internal clock period.
The PCMCIA cycle timing factors, in terms of the number of internal clocks, are calculated as
follows:
S = (Npres × Nval) + 1
C = (Npres × Nval) + 1
R = (Npres × Nval) + 1
Npres and Nval are the specific selected prescalar and multiplier value from the timer set’s Setup,
Command, and Recovery Timing registers (see “Timing Registers” on page 87 for description of
these registers).
From this, a PCMCIA cycle’s Setup, Command, and Recovery time for the selected timer set are
calculated as follows:
Minimum Setup time = (S
× Tcp) 20 ns
Minimum Command time = (C
× Tcp) 20 ns
Minimum Recovery time = (R
× Tcp) 20 ns
Tcp is two times the period of the PCI bus clock connected to the PD6729 PCI_CLK pin.
If PCI_CLK operates at 33 MHz, then:
Tcp = 60 ns
The timing diagrams that follow were derived for a PD6729 using the PCI clock at 33 MHz. The
examples are for the default values of the Timing registers for Timer Set 0, as follows:
Thus the minimum times for the default values are as follows:
Minimum Setup time = (S
× Tcp) 20 ns = {[(1 × 1) + 1] × 60 ns} 20 ns = 100 ns
Minimum Command time = (C
× Tcp) 20 ns = {[(1 × 5) + 1] × 60 ns} 20 ns = 340 ns
Minimum Recovery time = (R
× Tcp) 20 ns = {[(1 × 0) + 1] × 60 ns} 30 ns = 30 ns
Timing Register Name
(Timer Set 0)
Index
Value
(Default)
Resultant
Npres
Resultant Nval
Setup Timing 0
3Ah
01h
1
Command Timing 0
3Bh
05h
1
5
Recovery Timing 0
3Ch
00h
1
0
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