參數(shù)資料
型號: SPD6729QCE
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: PCMCIA BUS CONTROLLER, PQFP208
封裝: MQFP-208
文件頁數(shù): 82/116頁
文件大?。?/td> 1442K
代理商: SPD6729QCE
PD6729 — PCI-to-PC Card (PCMCIA) Controller
68
Datasheet
23h
System Memory Map 2 End Address High
2Bh
System Memory Map 3 End Address High
33h
System Memory Map 4 End Address High
Bits 3-0: End Address 23-20
This field contains the most-significant four bits of the End Address. See the description of the End
Address field associated with bits 7-0 of the System Memory Map 0-4 End Address Low
register. Note that the upper memory addresses are stored in the System Memory Map Upper
Address register.
Bits 7-6: Card Timer Select
This field selects the timer set. Timer Set 0 and 1 reset to values compatible with standard PCI and
three-wait-state cycles (see “Setup Timing 0-1” on page 87).
9.5
Card Memory Map 0-4 Offset Address Low
There are five separate Card Memory Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index
(Socket A)Card Memory Map Offset address Low
14h
Card Memory Map 0 Offset Address Low
1Ch
Card Memory Map 1 Offset Address Low
24h
Card Memory Map 2 Offset Address Low
2Ch
Card Memory Map 3 Offset Address Low
34h
Card Memory Map 4 Offset Address Low
Bits 7-0: Offset Address 19-12
This register contains the least-significant byte of the quantity that will be added to the system
memory address that determines where in the PCMCIA card’s memory map the memory access
will occur.
00
Selects Timer Set 0.
01
Selects Timer Set 1.
10
Selects Timer Set 1.
11
Selects Timer Set 1.
Register Name: Card Memory Map 0-4 Offset Address Low
Index: 14h, 1Ch, 24h, 2Ch, 34h
Register Per: socket
Register Compatibility Type: 365
Bit 7Bit 6Bit 5Bit 4Bit 3
Bit 2Bit 1
Bit 0
Offset Address 19-12
RW:00000000
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