參數(shù)資料
型號: SPD6729QCE
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: PCMCIA BUS CONTROLLER, PQFP208
封裝: MQFP-208
文件頁數(shù): 103/116頁
文件大小: 1442K
代理商: SPD6729QCE
PCI-to-PC Card (PCMCIA) Controller — PD6729
Datasheet
87
11.0
Timing Registers
The following information about the timing registers is important:
All timing registers take effect immediately and should only be changed when the FIFO is
Selection of Timer Set 0 or Timer Set 1 register sets is controlled by I/O Window Control,
11.1
Setup Timing 0-1
There are two separate Setup Timing registers, each with identical fields. These registers are
located at the following indexes:
Index
(Socket A)Setup Timing
3Ah
Setup Timing 0
3Dh
Setup Timing 1
The Setup Timing register for each timer set controls how long a PCMCIA cycle’s command (that
is, -OE, -WE, -IORD, -IOWR; see Table 2 on page 18) setup time will be, in terms of the number
of internal clock cycles.
The overall command setup timing length S is programmed by selecting a 2-bit prescaling value
(bits 7-6 of this register) representing weights of 1, 16, 256, or 4096, and then selecting a multiplier
value (bits 5-0) to which that prescalar is multiplied to produce the overall command setup timing
length according to the following formula:
S = (Npres × Nval) + 1
The value of S, representing the number of clock cycles for command setup, is then multiplied by
the clock period of the internal clock driving the PC card socket interface to determine the actual
command setup time (see “PCMCIA Bus Timing Calculations” on page 101 for further
discussion).
Bits 5-0: Setup Multiplier Value
This field indicates an integer value Nval from 0 to 63; it is combined with a prescalar value (bits
7-6) to control the length of setup time before a command becomes active.
Register Name: Setup Timing 0-1
Index: 3Ah, 3Dh
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Setup Prescalar Select
Setup Multiplier Value
RW:00
RW:000001
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