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參數(shù)資料
| 型號(hào)： | SPD6729QCE |
| 廠商： | INTEL CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PQFP208 |
| 封裝： | MQFP-208 |
| 文件頁數(shù)： | 25/116頁 |
| 文件大?。?/td> | 1442K |
| 代理商： | SPD6729QCE |
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PD6729 — PCI-to-PC Card (PCMCIA) Controller
16
Datasheet
TRDY#
Target Ready: This output indicates the PD6729’s
ability to complete the current data phase of the
transaction. TRDY# is used in conjunction with
IRDY#.
30
1
TO
4
PCI
Spec.
STOP#
Stop: This output indicates the current target is
requesting the master to stop the current transaction.
32
1
TO
4
PCI
Spec.
IDSEL
Initialization Device Select: This input is used as a
chip select during configuration read and write
transactions. This is a point-to-point signal. The
PD6729 must be connected to its own unique IDSEL
line (from the PCI bus arbiter or one of the high-order
AD bus pins).
15
1
I
––
DEVSEL#
Device Select: The PD6729 drives this output active
(low) when it has decoded the PCI address as one
that it is programmed to support, thereby acting as
the target for the current PCI cycle.
31
1
TO
4
PCI
Spec.
PERR#
Parity Error: The PD6729 drives this output active
(low) if it detects a data parity error during a write
phase.
33
1
TO
4
PCI
Spec.
SERR#
System Error: This output is pulsed by the PD6729
to indicate an address parity error.
34
1
OD
4
PCI
Spec.
PAR
Parity: This pin is sampled the clock cycle after
completion of each corresponding address or write
data phase. For read operations this pin is driven
from the cycle after TRDY# is asserted until the cycle
after completion of each data phase. It ensures even
parity across AD[31:0] and C/BE[3:0]#.
35
1
I/O
4
PCI
Spec.
PCI_CLK
PCI Clock: This input provides timing for all
transactions on the PCI bus to and from the PD6729.
All PCI bus interface signals described in this table
(Table 1), except RST#, INTA#, INTB#, INTC#, and
INTD#, are sampled on the rising edge of PCI_CLK;
and all PD6729 PCI bus interface timing parameters
are defined with respect to this edge. This input can
be operated at frequencies from 0 to 33 MHz.
11
I
––
RST#
Device Reset: This input is used to initialize all
registers and internal logic to their reset states and
place most PD6729 pins in a high-impedance state.
207
1
I
––
IRQ15/
RI_OUT*
Interrupt Request 15 / Ring Indicate Out: This
output can be used either as an interrupt output
(usually the system’s IRQ15 interrupt line), or if Misc
Control 2 register bit 7 is a ‘1’, as a ring indicate
output from a socket’s BVD1/-STSCHG/-RI input.
63
1
TO
4
2 mA
IRQ14/
EXT_CLK
Interrupt Request 14 / External Clock: This pin can
be used either as an interrupt output (usually the
system’s IRQ14 interrupt line), or if Misc Control 2
register bit 0 is a ‘1’, as an alternate external clock
input that will provide the internal clock to the PD6729
for PCMCIA cycle timing when the PCI bus is not
active.
62
1
I/O
4
2 mA
Table 1.
PCI Bus Interface Pins (Sheet 2 of 3)
Pin Name
Description
Pin Number
Qty.
I/O
Pwr.
Drive
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPD6730QCB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SPD6832QCB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| SPD73 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Shielded Surface Mount Inductors |
| SPD73-103M | 功能描述:固定電感器 10uH 20% .067ohm Shield Choke SMT Pwr RoHS:否 制造商:AVX 電感:10 uH 容差:20 % 最大直流電流:1 A 最大直流電阻:0.075 Ohms 工作溫度范圍:- 40 C to + 85 C 自諧振頻率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接類型:SMD/SMT 封裝 / 箱體:6.6 mm x 4.45 mm |
| SPD73-103MTR | 功能描述:固定電感器 10 UH 20% RoHS:否 制造商:AVX 電感:10 uH 容差:20 % 最大直流電流:1 A 最大直流電阻:0.075 Ohms 工作溫度范圍:- 40 C to + 85 C 自諧振頻率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接類型:SMD/SMT 封裝 / 箱體:6.6 mm x 4.45 mm |
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