參數(shù)資料
型號: SPD6729QCE
廠商: INTEL CORP
元件分類: 總線控制器
英文描述: PCMCIA BUS CONTROLLER, PQFP208
封裝: MQFP-208
文件頁數(shù): 23/116頁
文件大?。?/td> 1442K
代理商: SPD6729QCE
PD6729 — PCI-to-PC Card (PCMCIA) Controller
14
Datasheet
An asterisk (*) at the end of a pin name indicates an active-low signal that is a general-
interface for the PD6729.
Pins marked with a dagger () in the pin description tables can be switched between CMOS
and TTL input levels when CORE_VDD is powered at 5 volts. All other pins use CMOS input
levels when CORE_VDD is powered at 5 volts and TTL input levels when powered at 3.3
volts.
A pin name ending in bracketed digits separated by a colon [n:n] indicates a multi-pin bus.
The pin number (Pin Number) column indicates the package pin that carries the listed signal.
Note that multi-pin buses are listed with the first pin number corresponding to the most-
significant bit of the bus. For example, pin numbers 4-5, 7-12, 16-20, 22-24, 38-43, 45-46, 48-
49, 51-55, and 57 associated with PCI Bus Address Input and Data Input/Output pins
AD[31:0] indicate that:
— AD[31] is pin 4
— AD[1] is pin 55
— AD[0] is pin 57
The quantity (Qty.) column indicates the number of pins used (per socket where applicable).
The I/O-type code (I/O) column indicates the input and output configurations of the pins on
the PD6729. The possible types are defined below.
The power-type code (Pwr.) column indicates the output drive power source for an output pin
or the pull-up power source for an input pin on the PD6729. The possible types are defined
below.
I/O Type
Description
I
Input pin
I-PU
Input pin with an internal pull-up resistor
O
Constant-driven, output pin
I/O
Input/output pin
OD
Open-drain output pin
TO
Three-state output pin
TO-PU
Three-state output pin with internal pull-
up resistor
PW
Power or ground pin
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