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參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁(yè)數(shù)： | 90/211頁(yè) |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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10
EPSON
S1C8F626 TECHNICAL MANUAL
4 INITIAL RESET
4 INITIAL RESET
Initial reset in the S1C8F626 is required in order to initialize circuits. This section of the Manual
contains a description of initial reset factors and the initial settings for internal registers, etc.
4.1 Initial Reset Factors
There are two initial reset factors for the S1C8F626
as shown below.
(1)
_________
External initial reset by the RESET terminal
(2) External initial reset by the simultaneous LOW
level input at input port terminals K00–K03
(software selectable)
Figure 4.1.1 shows the configuration of the initial
reset circuit.
The CPU and peripheral circuits are initialized by
means of initial reset factors. When the factor is
canceled, the CPU commences reset exception
processing. (See the "S1C88 Core CPU Manual".)
When this occurs, the reset exception processing
vector, Bank 0, 000000H–000001H from program
memory is read out and the program (initialization
routine) which begins at the readout address is
executed.
____________
4.1.1 RESET terminal
Initial reset can be done by externally inputting a
_________
LOW level to the RESET terminal.
_________
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset. (See Section 9.6, "AC
Characteristics".)
_________
The RESET terminal is equipped with a pull-up
resistor.
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is
to input a LOW level simultaneously to the input
ports (K00–K03) selected with software. Since there
is a built-in time authorize circuit, be sure to
maintain the designated input port terminal at
LOW level for 65536/fOSC1 seconds (two seconds
when the oscillation frequency is fOSC1 = 32.768
kHz) or more to perform the initial reset by means
of this function. The combination of input ports
(K00–K03) that can be selected with software
(KEYR0–KEYR1 registers) are as follows:
Multiple key entry reset
Not use
(KEYR0–KEYR1 = 0)
K00 & K01
(KEYR0–KEYR1 = 1)
K00 & K01 & K02
(KEYR0–KEYR1 = 2)
K00 & K01 & K02 & K03 (KEYR0–KEYR1 = 3)
For instance, let's say that "K00 & K01 & K02 &
K03" is selected, when the input level at input ports
K00–K03 is simultaneously LOW, initial reset will
take place. Refer to Section 5.5, "Input Ports", for
details of the KEYR0–KEYR1 registers.
Notes: When using the multiple-key entry reset
function, make sure that the designated
input ports do not simultaneously switch to
LOW level while the system is in normal
operation.
The multiple-key entry reset function
cannot be used for power-on reset as it
must be enabled with software.
The multiple-key entry reset function
cannot be used in SLEEP mode.
OSC1
OSC2
OSC3
OSC4
RESET
VDD
fOSC1/256
fOSC3/1024
fOSC1
fOSC3
OSC1
oscillation circuit
Reset pulse
delay circuit
Divider
K00
K01
K02
K03
OSC3
oscillation circuit
Divider
Operating clock status
CPU-reset-
release clock
A
CPU reset
System reset
R
S
Q
Input port K00
Input port K01
Input port K02
Input port K03
Time
authorize
circuit
Multiple key
entry reset
control
circuit
KEYR0–1
Fig. 4.1.1 Configuration of initial reset circuit
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