
32
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)
5.3.3 Control of watchdog timer
Table 5.3.3.1 shows the control bits for the watchdog timer.
Table 5.3.3.1 Watchdog timer control bits
SR R/W
Address Bit
Name
Function
Comment
10
00FF40 D7
D6
D5
D4
D3
D2
D1
D0
WDEN
FOUT2
FOUT1
FOUT0
WDRST
TMRST
TMRUN
Constantly "0" when
being read
1
0
–
0
R/W
W
R/W
Enable
On
Reset
Run
Disable
Off
No operation
Stop
Watchdog timer enable
FOUT frequency selection
FOUT output control
Watchdog timer reset
Clock timer reset
Clock timer Run/Stop control
FOUTON
FOUT2
1
0
FOUT1
1
0
1
0
FOUT0
1
0
1
0
1
0
1
0
Frequency
fOSC3 / 8
fOSC3 / 4
fOSC3 / 2
fOSC3 / 1
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
WDEN: 00FF40HD7
Selects whether the watchdog timer is used
(enabled) or not (disabled).
When "1" is written: Enabled
When "0" is written: Disabled
Reading:
Valid
When "1" is written to the WDEN register, the
watchdog timer starts count operation. When "0" is
written, the watchdog timer does not count and
_______
does not generate the interrupt (NMI).
At initial reset, this register is set to "1".
WDRST: 00FF40HD2
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading:
Constantly "0"
By writing "1" to WDRST, the watchdog timer is
reset, after which it is immediately restarted.
Writing "0" will mean no operation.
Since WDRST is for writing only, it is constantly set
to "0" during readout.
5.3.4 Programming notes
(1) When the watchdog timer is being used, the
software must reset it within 4-second cycles
(when fOSC1 is 32.768 kHz).
(2) Do not execute the SLP instruction for 2 msec
_______
after a NMI interrupt has occurred (when fOSC1
is 32.768 kHz).
(3) Because the watchdog timer is set in operation
state by initial reset, set the watchdog timer to
disabled state (not used) before generating an
_______
interrupt (NMI) if it is not used.