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| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁(yè)數(shù)： | 17/211頁(yè) |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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S1C8F626 TECHNICAL MANUAL
EPSON
105
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
PRPRT0: 00FF14HD3
PRPRT1: 00FF14HD7
PRPRT2: 00FF15HD3
PRPRT3: 00FF15HD7
PRPRT4: 00FF18HD3
PRPRT5: 00FF18HD7
PRPRT6: 00FF19HD3
PRPRT7: 00FF19HD7
Controls the clock supply of each timer (when
internal clock is used).
When "1" is written: ON
When "0" is written: OFF
Reading:
Valid
By writing "1" to the PRPRTx register, the clock
that is selected with the PSTx register is output to
Timer x.
When "0" is written, the clock is not output.
At initial reset, the this register is set to "0" (OFF).
RDR00–RDR07: 00FF32H
RDR10–RDR17: 00FF33H
RDR20–RDR27: 00FF3AH
RDR30–RDR37: 00FF3BH
RDR40–RDR47: 00FFB2H
RDR50–RDR57: 00FFB3H
RDR60–RDR67: 00FFBAH
RDR70–RDR77: 00FFBBH
Sets the initial value for the counter of each timer.
Each counter loads the reload data set in this
register and counts using it as the initial value.
The reload data set in this register is loaded into
the counter when "1" is written to PSETx, or when
a counter underflow occurs.
This register can also be read.
At initial reset, this register is set to "FFH".
CDR00–CDR07: 00FF34H
CDR10–CDR17: 00FF35H
CDR20–CDR27: 00FF3CH
CDR30–CDR37: 00FF3DH
CDR40–CDR47: 00FFB4H
CDR50–CDR57: 00FFB5H
CDR60–CDR67: 00FFBCH
CDR70–CDR77: 00FFBDH
Sets the compare data for each timer.
The timer compares the data set in this register
with the corresponding counter data, and outputs
the compare match signals when they are the
same. The compare match signal controls the
interrupt and the TOUT output waveform.
This register can also be read.
At initial reset, this register is set to "00H".
PTM00–PTM07: 00FF36H
PTM10–PTM17: 00FF37H
PTM20–PTM27: 00FF3EH
PTM30–PTM37: 00FF3FH
PTM40–PTM47: 00FFB6H
PTM50–PTM57: 00FFB7H
PTM60–PTM67: 00FFBEH
PTM70–PTM77: 00FFBFH
The counter data of each timer can be read.
Data can be read at any given time. However, in
the 16-bit mode, reading PTM(L) does not latch the
Timer(H) counter data in PTM(H). To avoid
generating a borrow from Timer(L) to Timer(H),
read the counter data after stopping the timer by
writing "0" to PTRUN(L).
PTMx can only be read, so writing operation is
invalid.
At initial reset, PTMx is set to "FFH".
PSET0: 00FF30HD1
PSET1: 00FF31HD1
PSET2: 00FF38HD1
PSET3: 00FF39HD1
PSET4: 00FFB0HD1
PSET5: 00FFB1HD1
PSET6: 00FFB8HD1
PSET7: 00FFB9HD1
Presets the reload data to the counter.
When "1" is written: Preset
When "0" is written: Invalid
Reading:
Always "0"
Writing "1" to PSETx presets the reload data in the
RDRx register to the counter of Timer x. When the
counter of Timer x is in RUN status, the counter
restarts immediately after presetting.
In the case of STOP status, the counter maintains
the preset data.
No operation results when "0" is written.
In the 16-bit mode, writing "1" to PSET(H) is
invalid because 16-bit data is preset by PSET(L)
only.
PSETx is only for writing, and it is always "0"
during reading.
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