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參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 158/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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42
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
EK00–EK07: 00FF24H
How interrupt generation to the CPU is permitted
or prohibited.
When "1" is written: Interrupt permitted
When "0" is written: Interrupt prohibited
Reading:
Valid
EK0x is the interrupt enable register which
correspond to the input port K0x.
Interrupt is permitted in those terminals set to "1"
and prohibited in those set to "0".
At initial reset, this register is set to "0" (interrupt
prohibited).
FK00–FK07: 00FF28H
Indicates the generation state for an input interrupt.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Reset factor flag
When "0" is written: Invalid
The interrupt factor flag FK0x corresponds to K0x is
set to "1" by the occurrence of an interrupt
generation condition.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is all reset to "0".
KEYR0, KEYR1: 00FF5CHD0, D1
Configures the multiple-key entry reset function.
Table 5.5.5.5 Multiple-key entry reset configuration
KEYR1
1
0
Port combination
K00 & K01 & K02 & K03
K00 & K01 & K02
K00 & K01
Not used
KEYR0
1
0
1
0
When "Not used" is selected, the multiple-key entry
reset function is disabled. When a port combination
is selected, the IC will be reset when the selected
ports are set to LOW simultaneously.
At initial reset, this register is set to "0" (not used).
5.5.6 Programming notes
(1) When changing the input terminal from LOW
level to HIGH with the built-in pull-up resistor,
a delay in the waveform rise time will occur
depending on the time constant of the pull-up
resistor and the load capacitance of the
terminal. It is necessary to set an appropriate
wait time for introduction of an input port. In
particular, special attention should be paid to
key scan for key matrix formation. Make this
wait time the amount of time or more calculated
by the following expression.
Wait time = RIN x (CIN + load capacitance on the
board) x 1.6 [sec]
RIN: Pull up resistance Max. value
CIN: Terminal capacitance Max. value
(2) Be sure to disable interrupts before changing
the contents of the CTK0x register. Unnecessary
interrupts may occur if the register is changed
when the corresponding input port interrupts
have been enabled by the interrupt enable
register EK0x.
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