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參數(shù)資料
| 型號： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 191/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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72
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
SCS00, SCS01: 00FF48HD3, D4
SCS10, SCS11: 00FF4CHD3, D4
Select the clock source according to Table 5.7.10.3.
Table 5.7.10.3 Clock source selection
SCSx1
1
0
SCSx0
1
0
1
0
Clock source
Programmable timer 1 (Ch.0)
Programmable timer 7 (Ch.1)
fOSC3 / 4
fOSC3 / 8
fOSC3 / 16
SCSx0 and SCSx1 can also be read out.
In the clock synchronous slave mode, setting of this
register is invalid.
At initial reset, this register is set to "0" (fOSC3/16).
SDP0: 00FF4BHD0
SDP1: 00FF4FHD0
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading:
Valid
Select whether the data input/output permutation
will be MSB first or LSB first.
At initial reset, SDPx is set to "0" (LSB first).
STPB0: 00FF4BHD1
STPB1: 00FF4FHD1
Selects the stop bit length for asynchronous data
transfer.
When "1" is written: 2 bits
When "0" is written: 1 bit
Reading:
Valid
STPBx is the stop bit select register that is effective
in asynchronous mode. When "1" is written to
STPBx, the stop bit length is set to 2 bits, and when
"0" is written, it is set to 1 bit.
In clock synchronous mode, no start/stop bits can
be added to transfer data. Therefore, setting STPBx
becomes invalid.
At initial reset, STPBx is set to "0" (1 bit).
EPR0: 00FF48HD6
EPR1: 00FF4CHD6
Selects the parity function.
When "1" is written: With parity
When "0" is written: Non parity
Reading:
Valid
Selects whether or not to check parity of the
received data and to add a parity bit to the trans-
mitting data. When "1" is written to EPRx, the most
significant bit of the received data is considered to
be the parity bit and a parity check is executed. A
parity bit is added to the transmitting data. When
"0" is written, neither checking is done nor is a
parity bit added.
Parity is valid only in asynchronous mode and the
EPRx setting becomes invalid in the clock synchro-
nous mode.
At initial reset, EPRx is set to "0" (non parity).
PMD0: 00FF48HD5
PMD1: 00FF4CHD5
Selects odd parity/even parity.
When "1" is written: Odd parity
When "0" is written: Even parity
Reading:
Valid
When "1" is written to PMDx, odd parity is selected
and even parity is selected when "0" is written. The
parity check and addition of a parity bit is only
valid when "1" has been written to EPRx. When "0"
has been written to EPRx, the parity setting by
PMDx becomes invalid.
At initial reset, PMDx is set to "0" (even parity).
TXEN0: 00FF49HD0
TXEN1: 00FF4DHD0
Sets the serial interface to the transmitting enable
status.
When "1" is written: Transmitting enable
When "0" is written: Transmitting disable
Reading:
Valid
When "1" is written to TXENx, the serial interface
shifts to the transmitting enable status and shifts to
the transmitting disable status when "0" is written.
Set TXENx to "0" when making the initial settings
of the serial interface and similar operations.
At initial reset, TXENx is set to "0" (transmitting
disable).
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