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參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 156/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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S1C8F626 TECHNICAL MANUAL
EPSON
41
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
K00D–K07D: 00FF54H
Input data of input port terminal K0x can be read
out.
When "1" is read:
HIGH level
When "0" is read:
LOW level
Writing:
Invalid
The terminal voltage of each of the input port K00–
K07 can be directly read out as either a "1" for
HIGH (VDD) level or a "0" for LOW (VSS) level.
This bit is exclusively for readout and are not
usable for write operations.
IFLK00–IFLK07: 00FF5AH
Selects an input interface level.
When "1" is written: CMOS Schmitt level
When "0" is written: CMOS level
Reading:
Valid
IFLK0x is the input I/F level select register
corresponding to each input port K0x.
When "1" is written to IFLK0x, the corresponding
input port K0x is configured with a CMOS Schmitt
level interface. When "0" is written, the port is
configured with a CMOS level interface.
At initial reset, this register is set to "0" (CMOS
level).
PULK00–PULK07: 00FF56H
Controls the input pull-up resistor.
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading:
Valid
PULK0x is the pull-up control register
corresponding to the input port K0x that turns the
pull-up resistor built into the input port ON and
OFF.
When "1" is written to PULK0x, the corresponding
input port K0x is pulled up to high. When "0" is
written, the input port is not pulled up.
At initial reset, this register is set to "1" (Pull-up
ON).
KCP00–KCP07: 00FF52H
Sets the interrupt generation condition (interrupt
generation timing) for input port terminals K00–
K07.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading:
Valid
KCP0x is the input comparison register which
corresponds to the input port K0x. Interrupt in
those ports which have been set to "1" is generated
on the falling edge of the input and in those set to
"0" on the rising edge.
At initial reset, this register is set to "1" (falling
edge).
CTK00L–CTK02L: 00FF58HD0–D2
Sets the input level check time of the chattering-
eliminate circuit for the K00–K03 input port
interrupts as shown in Table 5.5.5.2.
Table 5.5.5.2 Setting the input level check time
CTK02L
1
0
CTK01L
1
0
1
0
CTK00L
1
0
1
0
1
0
1
0
Input level check time [sec]
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
Be sure to disable interrupts before changing the
contents of this register. Unnecessary interrupts
may occur if the register is changed when the
corresponding input port interrupts have been
enabled by the interrupt enable register EK0x.
At initial reset, this register is set to "0" (None).
CTK00H–CTK02H: 00FF58HD4–D6
Sets the input level check time of the chattering-
eliminate circuit for the K04–K07 input port
interrupts as shown in Table 5.5.5.3.
Table 5.5.5.3 Setting the input level check time
CTK02H
1
0
CTK01H
1
0
1
0
CTK00H
1
0
1
0
1
0
1
0
Input level check time [sec]
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
Be sure to disable interrupts before changing the
contents of this register. Unnecessary interrupt may
occur if the register is changed when the
corresponding input port interrupts have been
enabled by the interrupt enable register EK0x.
At initial reset, this register is set to "0" (None).
PK00, PK01: 00FF20HD6, D7
Sets the input interrupt priority level. PK00 and
PK01 are the interrupt priority registers
corresponding to the input interrupts.
Table 5.5.5.4 shows the interrupt priority level
which can be set by this register.
Table 5.5.5.4 Interrupt priority level settings
PK01
PK00
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
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