
S1C8F626 TECHNICAL MANUAL
EPSON
5
1 INTRODUCTION
1.3.2 Pin description
Table 1.3.2.1 S1C8F626 pin description
VDD
VSS
VD1
VD2
VC1–VC5
CA–CG
OSC1
OSC2
OSC3
OSC4
K00–K03
K04
(EXCL0)
K05
(EXCL1)
K06
(EXCL2)
K07
(EXCL3)
P00–P07
P10
(SIN0)
P11
(SOUT0)
P12
(SCLK0)
P13
(SRDY0)
P14
(TOUT0/TOUT1)
P15
(TOUT2/TOUT3)
P16
(FOUT)
P17
(TOUT2/TOUT3)
P20
(SIN1)
P21
(SOUT1)
P22
(SCLK1)
P23
(SRDY1)
P24–P27
COM0–COM31
SEG0–SEG95
DMOD
DCLK
DRXD
DTXD
RESET
TEST
TEST1–TEST3
Pin name
I/O
Function
C2, U1
B8, E1, U2
E2
B7
C3, B3, A3, C4, B4
A4, C5, B5, A5, C6,
B6, A6
F1
F2
D1
D2
J1
H4
H3
H2
T2, T1, R3, R2,
R1, P4, P3, P2
P1
N4
N3
N2
N1
M4
M3
M2
M1
L4
L3
L2
L1, K4, K3, K2
1
2
G1
H1
G2
G3
F4
F3
C8, D8, A7
–
I
O
I
O
I
(I)
I
(I)
I
(I)
I
(I)
I/O
(I)
I/O
(O)
I/O
(I/O)
I/O
(O)
I/O
(O)
I/O
(O)
I/O
(O)
I/O
(O)
I/O
(I)
I/O
(O)
I/O
(I/O)
I/O
(O)
I/O
O
I
O
I
I/O
Initial status3
–
I
O
I
O
I (Pull-up)
O (L)
I (Pull-up)
O (H)
I (Pull-up)
–
Power supply (+) terminal
Power supply (GND) terminal
Internal logic system and oscillation system voltage
regulator output terminals
LCD circuit power voltage booster output terminal
LCD drive voltage output terminals
LCD and power voltage booster capacitor connection
terminals
OSC1 oscillation input terminal (crystal oscillation)
OSC1 oscillation output terminal
OSC3 oscillation input terminal
(crystal/ceramic or CR oscillation)
OSC3 oscillation output terminal
Input port terminals
Input port terminal
(Programmable timer external clock input terminal)
Input port terminal
(Programmable timer external clock input terminal)
Input port terminal
(Programmable timer external clock input terminal)
Input port terminal
(Programmable timer external clock input terminal)
I/O port terminals
I/O port terminal
(Serial I/F Ch. 0 data input terminal)
I/O port terminal
(Serial I/F Ch. 0 data output terminal)
I/O port terminal
(Serial I/F Ch. 0 clock I/O terminal)
I/O port terminal
(Serial I/F Ch. 0 ready signal output terminal)
I/O port terminal
(Programmable timer 0/1 output terminal)
I/O port terminal
(Programmable timer 2/3 output terminal)
I/O port terminal
(FOUT clock output terminal)
I/O port terminal
(Programmable timer 2/3 inverted output terminal)
I/O port terminal
(Serial I/F Ch. 1 data input terminal)
I/O port terminal
(Serial I/F Ch. 1 data output terminal)
I/O port terminal
(Serial I/F Ch. 1 clock I/O terminal)
I/O port terminal
(Serial I/F Ch. 1 ready signal output terminal)
I/O port terminals
LCD common output terminals
LCD segment output terminals
PROM programming control terminal
Clock input terminal for PROM programming
Serial data input terminal for PROM programming
Serial data output terminal for PROM programming
Initial reset input terminal
Test input terminal
Test terminals (open TEST1 and TEST3, and connect
TEST2 to VDD during normal operation)
1 COM0–COM31:
2 SEG0–SEG95:
3 (Pull-up): pulled up, (H): high-level output, (L): low-level output
W4, V4, U4, W5, V5, U5, W6, V6, U6, W7, V7, U7, T7, W8, V8, U8, A8, D9, C9, B9, A9, D10, C10, B10, A10,
D11, C11, B11, A11, D12, C12, B12
T8, W9, V9, U9, T9, W10, V10, U10, T10, W11, V11, U11, T11, W12, V12, U12, T12, W13, V13, U13, T13, W14,
V14, U14, T14, W15, V15, U15, W16, V16, W17, V17, U18, T19, T18, T17, R19, R18, R17, P19, P18, P17, N19,
N18, N17, M19, M18, M17, M16, L19, L18, L17, L16, K19, K18, K17, K16, J19, J18, J17, J16, H19, H18, H17, H16,
G19, G18, G17, G16, F19, F18, F17, F16, E19, E18, E17, D19, D18, D17, C19, C18, B17, A16, B16, C16, A15, B15,
C15, A14, B14, C14, A13, B13, C13, D13, A12
Note: In the S1C8F626, the port configured for output cannot be set in high-impedance status.
Pin No. (VFBGA)
Pin No. (QFP)
112, 157
89, 115, 158
116
93
105–101
100–94
117
118
113
114
132–129
128
127
126
125
156–149
148
147
146
145
144
143
142
141
140
139
138
137
136–133
166–181, 88–73
182–213, 4–52, 58–72
121
124
122
123
120
119
90–92