S1C8F626 TECHNICAL MANUAL
EPSON
83
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer)
5.9.3 Interrupt function
The stopwatch timer can generate an interrupt by
each of the 100 Hz (approximately 100 Hz), 10 Hz
(approximately 10 Hz) and 1 Hz signals.
Figure 5.9.3.1 shows the configuration of the
stopwatch timer interrupt circuit.
The corresponding factor flags FSW100, FSW10 and
FSW1 are respectively set to "1" at the falling edge
of the 100 Hz, 10 Hz and 1 Hz signal and an
interrupt is generated. Interrupt can be prohibited
by the setting of the interrupt enable registers
ESW100, ESW10 and ESW1 corresponding to each
interrupt factor flag.
In addition, a priority level of the stopwatch timer
interrupt for the CPU can be optionally set at levels
0 to 3 by the interrupt priority registers PSW0 and
PSW1.
For details on the above mentioned interrupt
control registers and the operation following
generation of an interrupt, see "5.14 Interrupt and
Standby Status".
The exception processing vector addresses of each
interrupt factor are respectively set as shown
below.
100 Hz interrupt:
00002EH
10 Hz interrupt:
000030H
1 Hz interrupt:
000032H
Figure 5.9.3.2 shows the timing chart for the
stopwatch timer.
SWD0
SWD1
SWD2
SWD3
100 Hz interrupt
10 Hz interrupt
1/100 sec
counter
BCD data
SWD4
SWD5
SWD6
SWD7
1 Hz interrupt
1/10 sec
counter
BCD data
123456789012345678901234
0
Fig. 5.9.3.2 Stopwatch timer timing chart
Data
bus
Interrupt
request
Address
100 Hz falling edge
Interrupt factor
flag
FSW100
Address
Interrupt enable
register ESW100
Address
10 Hz falling edge
Interrupt factor
flag
FSW10
Address
Interrupt enable
register ESW10
Address
1 Hz falling edge
Interrupt factor
flag
FSW1
Address
Interrupt enable
register ESW1
Interrupt priority
level judgment
circuit
Address
Interrupt priority
register PSW0, PSW1
Fig. 5.9.3.1
Configuration of the stopwatch timer
interrupt circuit