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| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁(yè)數(shù)： | 152/211頁(yè) |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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S1C8F626 TECHNICAL MANUAL
EPSON
37
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
5.5 Input Ports (K ports)
5.5.1 Configuration of input ports
The S1C8F626 is equipped with 8 input port bits
(K00–K07) all of which are usable as general purpose
input port terminals with interrupt function.
K04–K07 terminals doubles as the external clock
(EXCL0–EXCL3) input terminal of the
programmable timer (event counter) with input
port functions sharing the input signal as is (see
"5.10 Programmable Timer").
The K00–K03 input port can be used for multiple-
key entry reset (see "4.1.2 Simultaneous LOW level
input at input port terminals K00–K03"). When the
multiple-key entry reset function is used, a port
combination used for resetting can be selected with
software.
Figure 5.5.1.1 shows the structure of the input port.
Input
interrupt
circuit
VDD
VSS
Data
bus
Kxx
KxxD
Address
Pull-up
control
register
Fig. 5.5.1.1 Structure of input port
Each input port terminal is directly connected via a
three-state buffer to the data bus. Furthermore, the
input signal state at the instant of input port
readout is read in that form as data.
5.5.2 Input interface level
The S1C8F626 input ports allow software to select
an input interface level. When the input I/F level
select register IFLK0x is set to "0", the
corresponding input port is configured with a
CMOS level interface. When IFLK0x is set to "1", the
port is configured with a CMOS Schmitt level
interface. At initial reset, all the ports are
configured with a CMOS level interface.
5.5.3 Pull-up control
The S1C8F626 input ports have a built-in pull-up
resistor and the resistor in each port is enabled or
disabled with software.
The pull-up resistor becomes effective by writing
"1" to the pull-up control register PULK0x that
corresponds to each port, and the input line is
pulled up. When "0" has been written, no pull-up is
done.
At initial reset, the pull-up control register is set to
"1" (pulled up).
The input port with a pull-up resistor suits input
from the push switch and key matrix.
When changing the input terminal from LOW level
to HIGH with the built-in pull-up resistor, a delay
in the waveform rise time will occur depending on
the time constant of the pull-up resistor and the
load capacitance of the terminal. It is necessary to
set an appropriate wait time for introduction of an
input port. In particular, special attention should be
paid to key scan for key matrix formation. Make
this wait time the amount of time or more calcu-
lated by the following expression.
Wait time = RIN x (CIN + load capacitance on the
board) x 1.6 [sec]
RIN: Pull up resistance Max. value
CIN: Terminal capacitance Max. value
The input port without a pull-up resistor is suits for
slide switch input and interfacing with other LSIs.
In this case, take care that a floating state does not
occur in input.
For unused ports, enable pull-up using the pull-up
control registers.
5.5.4 Interrupt function and input
comparison register
All the input ports (K00–K07) provide the interrupt
functions. The conditions for issuing an interrupt
can be set by the software.
When the interrupt generation condition set for a
terminal is met, the interrupt factor flag FK00–FK07
corresponding to the terminal is set at "1" and an
interrupt is generated.
Interrupt can be prohibited by setting the interrupt
enable registers EK00–EK07 for the corresponding
interrupt factor flags.
Furthermore, the priority level for input interrupt
can be set at the desired level (0–3) using the
interrupt priority registers PK00–PK01.
For details on the interrupt control registers for the
above and on operations subsequent to interrupt
generation, see "5.14 Interrupt and Standby Status".
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