
S1C8F626 TECHNICAL MANUAL
EPSON
31
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)
5.3 Watchdog Timer
5.3.1 Configuration of watchdog timer
The S1C8F626 is equipped with a watchdog timer
driven by OSC1 as source oscillation. The watchdog
timer must be reset periodically in software, and if
reset of more than 131072/fOSC1 seconds (4 seconds
when fOSC1 = 32.768 kHz) does not take place, a
non-maskable interrupt signal is generated and
output to the CPU. The watchdog timer starts
operating after initial reset, however, it can be
stopped by the software.
Figure 5.3.1.1 is a block diagram of the watchdog
timer.
By running watchdog timer reset during the main
routine of the program, it is possible to detect
program runaway as if watchdog timer processing
had not been applied. Normally, this routine is
integrated at points that are regularly being
processed.
Watchdog timer
enable signal
WDEN
fOSC1/128
fOSC1
Watchdog timer
reset signal
Non-maskable
interrupt (NMI)
Watchdog
timer
Divider
WDRST
OSC1
oscillation
circuit
The watchdog timer continues to operate during
HALT and when a HALT state is continuous for
longer than 131072/fOSC1 seconds, the CPU shifts to
exception processing.
During SLEEP, the watchdog timer is stopped.
5.3.2 Interrupt function
In cases where the watchdog timer is not periodi-
cally reset in software, the watchdog timer outputs
_______
an interrupt signal to the CPU's NMI (level 4) input.
Unmaskable and taking priority over other inter-
rupts, this interrupt triggers the generation of
exception processing. See the "S1C88 Core CPU
_______
Manual" for more details on NMI exception
processing.
This exception processing vector is set at 000004H.
Fig. 5.3.1.1 Block diagram of watchdog timer