
S1C8F626 TECHNICAL MANUAL
EPSON
59
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
When you have set in the master mode, control the
transfer by inputting the same signal from the slave
side using the input port or I/O port. At this time,
_________
since the SRDYx terminal is not set and instead
P13/P23 functions as the I/O port, you can apply
this port for said control.
■ Timing chart
The timing chart for the clock synchronous system
transmission is shown in Figure 5.7.6.4.
(a) Transmit timing for master mode
(b) Transmit timing for slave mode
(c) Receive timing for master mode
(d) Receive timing for slave mode
Fig. 5.7.6.4 Timing chart (clock synchronous system transmission, LSB first)
■
___________
Transmit/receive ready (SRDYx) signal
When this serial interface is used in the clock
synchronous slave mode (external clock input), an
_________
SRDYx signal is output to indicate whether or not
this serial interface can transmit/receive to the
master side (external serial input/output device).
_________
This signal is output from the SRDYx terminal and
when this interface enters the transmit or receive
enable (READY) status, it becomes "0" (LOW level)
and becomes "1" (HIGH level) when there is a
BUSY status, such as during transmit/receive
operation.
_________
The SRDYx signal changes the "1" to "0," immedi-
ately after writing "1" into the transmit control bit
TXTRGx or the receive control bit RXTRGx and
returns from "0" to "1", at the point where the first
synchronous clock has been input (falling edge).
SCLKx
TXTRGx (RD)
SOUTx
D0 D1 D2 D3 D4 D5 D6 D7
TXENx
Interrupt
TXTRGx (WR)
SCLKx
TXTRGx (RD)
SOUTx
D0 D1D2D3D4D5D6D7
TXENx
Interrupt
TXTRGx (WR)
SRDYx
SCLKx
RXTRGx (RD)
SINx
D0 D1 D2 D3 D4 D5 D6 D7
RXENx
Interrupt
RXTRGx (WR)
TRXDx
7F
1st data
SRDYx
7F
SCLKx
RXTRGx (RD)
SINx
D0 D1 D2 D3 D4 D5 D6 D7
RXENx
Interrupt
RXTRGx (WR)
TRXDx
7F
1st data