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參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁(yè)數(shù)： | 202/211頁(yè) |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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82
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer)
5.9 Stopwatch Timer
5.9.1 Configuration of stopwatch timer
The S1C8F626 has a built-in 1/100 sec and 1/10 sec
stopwatch timer. The stopwatch timer is composed
of a 4-bit 2 stage BCD counter (1/100 sec units and
1/10 sec units) that makes the 256 Hz signal that
divides the fOSC1 the input clock and it can read the
count data by software.
Figure 5.9.1.1 shows the configuration of the
stopwatch timer.
The stopwatch timer can be used as a timer differ-
ent from the clock timer and can easily realize
stopwatch and other such functions by software.
Figure 5.9.2.1 shows the count up pattern of the
stopwatch timer.
The feedback dividing circuit generates an approxi-
mate 100 Hz signal at 2/256 sec and 3/256 sec
intervals from a 256 Hz signal divided from fOSC1.
The 1/100 sec counter (SWD0–SWD3) generates an
approximate 10 Hz signal at 25/256 sec and 26/256
sec intervals by counting the approximate 100 Hz
signal generated by the feedback dividing circuit in
2/256 sec and 3/256 sec intervals. The count-up is
made approximately 1/100 sec counting by the 2/
256 sec and 3/256 sec intervals.
The 1/10 sec counter (SWD4–SWD7) generates a 1
Hz signal by counting the approximate 10 Hz
signal generated by the 1/100 sec counter at 25/256
sec and 26/256 sec intervals in 4:6 ratios.
The count-up is made approximately 1/10 sec
counting by 25/256 sec and 26/256 sec intervals.
5.9.2 Count up pattern
The stopwatch timer is respectively composed of the
4-bit BCD counters SWD0–SWD3 and SWD4–SWD7.
Data bus
Interrupt
request
Divider
256 Hz
Stopwatch timer reset
SWRUN
Stopwatch timer
SWD0–SWD7
1 Hz
SWRST
OSC1
oscillation
circuit
fOSC1
Stopwatch timer Run/Stop
Approximate 100 Hz
Approximate 10 Hz
Feedback
dividing circuit
Interrupt
control
circuit
1/100 sec
4-bit BCD counter
1/10 sec
4-bit BCD counter
Fig. 5.9.1.1
Configuration of
stopwatch timer
1/10 sec counter count-up pattern
26
256
0
26
256
1
25
256
2
25
256
3
26
256
4
26
256
5
25
256
6
25
256
7
26
256
8
26
256
90
Count value
Count clock
(Approximate 10 Hz signal)
Count time
(sec)
3
256
0
2
256
1
3
256
2
2
256
3
3
256
4
2
256
5
3
256
6
2
256
7
3
256
8
2
256
90
Count value
Count clock
(256 Hz)
Count time
(sec)
3
256
0
3
256
1
3
256
2
2
256
3
3
256
4
2
256
5
3
256
6
2
256
7
3
256
8
2
256
90
Count value
Count clock
(256 Hz)
Count time
(sec)
25
256
26
256
sec
1/100 sec counter count-up pattern 1
Approximate 10 Hz signal
1/100 sec counter count-up pattern 2
Approximate 10 Hz signal
1 Hz signal
26
256
x 6 +
25
256
x 4 = 1 sec
Fig. 5.9.2.1
Count-up pattern of stopwatch timer
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